阅读说明：本技术 一种半导体组件 (Semiconductor assembly ) 是由 周云 张野 曾昭孔 陈武伟 于 2021-09-16 设计创作，主要内容包括：本申请公开了一种半导体组件,半导体组件包括：基板；设置在所述基板上的至少两个芯片,所述芯片层叠设置,各所述芯片包括相背设置的第一表面和第二表面,所述第一表面上设置有若干个向所述第二表面方向延伸的容置槽；及若干个焊接件,设置于所述芯片第二表面的一侧,所述焊接件与所述容置槽一一对应；在任意相邻两所述芯片之间,上层的所述芯片的焊接件在下层的所述芯片的容置槽内焊接,以使两所述芯片之间能够电连接。本申请通过在芯片设置有容置槽,熔融态的焊接件填充于容置槽,保证熔融态的焊接件完全位于容置槽内,有利于避免相邻两个焊接件存在桥接的问题。(The application discloses semiconductor component, semiconductor component includes: a substrate; the chip stacking structure comprises at least two chips arranged on a substrate, wherein the chips are stacked, each chip comprises a first surface and a second surface which are arranged in a back-to-back mode, and a plurality of accommodating grooves extending towards the direction of the second surface are formed in the first surface; the welding pieces are arranged on one side of the second surface of the chip and correspond to the accommodating grooves one to one; between any two adjacent chips, the welding piece of the chip on the upper layer is welded in the accommodating groove of the chip on the lower layer, so that the two chips can be electrically connected. This application is through being provided with the storage tank at the chip, and the welding of melt state is filled in the storage tank, guarantees that the welding of melt state is located the storage tank completely, is favorable to avoiding two adjacent welding to have the problem of bridging.)

1. A semiconductor assembly, comprising:

a substrate;

the chip stacking structure comprises at least two chips arranged on a substrate, wherein the chips are stacked, each chip comprises a first surface and a second surface which are arranged in a back-to-back mode, and a plurality of accommodating grooves extending towards the direction of the second surface are formed in the first surface; and

the welding pieces are arranged on one side of the second surface of the chip and correspond to the accommodating grooves one to one;

between any two adjacent chips, the welding piece of the chip on the upper layer is welded in the accommodating groove of the chip on the lower layer, so that the two chips can be electrically connected.

2. The semiconductor assembly of claim 1, wherein the solder of the upper chip is in a position-limited fit with the receiving slot of the lower chip.

3. The semiconductor assembly of claim 2, wherein the solder part of the upper chip is disposed in the receiving slot of the lower chip, and a highest point of the solder part is lower than or flush with an opening of the receiving slot.

4. The semiconductor assembly of claim 1, wherein the opening of the receiving groove is flared.

5. The semiconductor assembly of claim 1, wherein the plurality of receiving slots are arranged at equal intervals or at unequal intervals.

6. The semiconductor assembly according to any one of claims 1 to 5, further comprising a plurality of conductive members, wherein the conductive members correspond one-to-one to the solder members, and the solder members are disposed on one side of the second surface through the conductive members.

7. The semiconductor assembly according to claim 6, wherein the chip is further provided with a through hole, one end of the through hole communicates with the accommodating groove, the other end of the through hole is located on the second surface, the conductive member is provided on the through hole, and the solder member is connected to an end portion of the conductive member close to the second surface.

8. The semiconductor assembly according to claim 6, wherein the inner wall of the receiving groove is provided with a conductive layer, and the conductive layer is connected to the conductive member.

9. The semiconductor device as claimed in claim 7, wherein one end of the conductive member protrudes from the through hole corresponding to the conductive member and is connected to the solder member.

10. The semiconductor assembly of claim 7, wherein the other end of the conductive member is flush with the bottom of the receiving groove corresponding to the conductive member.

Technical Field

The present invention relates generally to the field of chip manufacturing technology, and more particularly to a semiconductor assembly.

Background

The development of microelectronic technology has led to the development of packaging technology towards miniaturization, multi-functionalization, low power consumption and high performance. The traditional two-dimensional packaging mode is difficult to meet the requirements, and a 2.5D/3D packaging mode begins to appear.

The common 2.5D/3D packaging mode refers to a packaging technology in which more than two chips are stacked in the same package in the vertical direction without changing the area of the package, so that the multifunction and miniaturization of the chips are realized.

The packaging mode has the problem of solder joint bridging.

Disclosure of Invention

In view of the above-mentioned drawbacks and deficiencies of the prior art, it is desirable to provide a semiconductor assembly.

The present application provides a semiconductor assembly, comprising:

a substrate;

the chip stacking structure comprises at least two chips arranged on a substrate, wherein the chips are stacked, each chip comprises a first surface and a second surface which are arranged in a back-to-back mode, and a plurality of accommodating grooves extending towards the direction of the second surface are formed in the first surface; and

the welding pieces are arranged on one side of the second surface of the chip and correspond to the accommodating grooves one to one;

between any two adjacent chips, the welding piece of the chip on the upper layer is welded in the accommodating groove of the chip on the lower layer, so that the two chips can be electrically connected.

As an optional scheme, the welding piece of the chip on the upper layer is in limit fit with the accommodating groove of the chip on the lower layer.

As an optional scheme, the welding part of the chip on the upper layer is disposed in the accommodating groove of the chip on the lower layer, and the highest point of the welding part is lower than or flush with the opening of the accommodating groove.

As an optional scheme, the opening of the accommodating groove is in a flaring shape.

As an optional scheme, a plurality of the accommodating grooves are arranged at equal intervals or at unequal intervals.

Optionally, the welding device further comprises a plurality of conductive pieces, the conductive pieces correspond to the welding pieces one to one, and the welding pieces are arranged on one side of the second surface through the conductive pieces.

As an optional scheme, the chip is further provided with a through hole, one end of the through hole is communicated with the accommodating groove, the other end of the through hole is located on the second surface, the conductive piece is arranged on the through hole, and the welding piece is connected to the end portion, close to the second surface, of the conductive piece.

As an optional scheme, a conductive layer is arranged on the inner wall of the accommodating groove, and the conductive layer is connected with the conductive piece.

Optionally, one end of the conductive member protrudes from the through hole corresponding to the conductive member and is connected to the solder member.

Optionally, the other end of the conductive member is flush with the bottom of the accommodating groove corresponding to the conductive member.

This application is through being provided with the storage tank at the chip, and the welding of melt state is filled in the storage tank, guarantees that the welding of melt state is located the storage tank completely, is favorable to avoiding two adjacent welding to have the problem of bridging. Before two adjacent chips are not connected, the limiting fit enables the welding part to be located in the accommodating groove, the degree of freedom of movement in the horizontal direction between the two chips is restrained, and deviation between the two adjacent chips is avoided.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 is a first schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

fig. 2 is a second schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

fig. 3 to 8 are schematic views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 9 is a first schematic diagram of an apparatus for die bonding according to an embodiment of the present invention;

fig. 10 is a second schematic diagram of an apparatus for die bonding according to an embodiment of the present invention;

fig. 11 is a third schematic diagram of an apparatus for die bonding according to an embodiment of the present invention.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

Fig. 1 shows a schematic structural diagram of a semiconductor component.

As shown in fig. 1, a semiconductor assembly includes a substrate 20 and at least two chips 10, the chips 10 may be stacked, and the stacked chips 10 are disposed on the substrate 20.

Each chip 10 comprises a first surface 101 back to the substrate 20 and a second surface 102 facing the substrate 20, the first surface 101 is provided with a plurality of accommodating grooves 11 recessed towards the substrate 20, one side of the second surface 102 is provided with a plurality of welding pieces 30, and the welding pieces 30 correspond to the accommodating grooves 11 one by one; between any two adjacent chips 10, the solder members 30 of the upper chip 10 are soldered in the receiving grooves 11 of the lower chip 10, so that the two chips 10 are electrically connected.

It should be noted that the substrate 20 provides electrical connection and support for the chip 10. A circuit layer is disposed on the substrate 20, and the substrate 20 includes a plurality of conductive connection lines 21. The solder 30 may be made of indium, copper, nickel, tin, or other suitable materials, and the solder 30 may be in a ball shape, a block shape, or other suitable shapes. At a preset temperature, the weldment 30 is able to change from a solid state to a molten state.

The first surface 101 is provided with a plurality of receiving grooves 11 recessed toward the substrate 20, and the plurality of receiving grooves 11 may be arranged at equal intervals M1 along a first direction perpendicular to the stacking direction of the chips 10. Correspondingly, one side of the second surface 102 is provided with a plurality of weldments 30, and the plurality of weldments 30 are arranged at equal intervals M2 along the first direction. The interval M1 is equal to the interval M2, the solder members 30 of the upper chip 10 face the receiving slots 11 of the lower chip 10, and the solder members 30 can be located in the receiving slots 11. The welding members 30 are welded in the accommodating groove 11, so that the molten welding members 30 can be filled in the accommodating groove 11, and the two adjacent welding members 30 are prevented from bridging. After the solder 30 is solidified, the two chips 10 are fixedly connected and electrically connected.

Of course, in other embodiments of the present invention, the plurality of receiving grooves 11 may also be arranged in a non-equidistant manner along the first direction, and correspondingly, the plurality of welding members 30 are also arranged in a non-equidistant manner along the first direction, and only the receiving grooves 11 and the welding members 30 need to be in one-to-one correspondence.

In the related art, a plurality of solder members 30 are disposed at equal intervals between two adjacent chips 10, and there is a problem of bridging between two adjacent solder members 30 at a predetermined temperature.

Based on this, the present application provides the above semiconductor device, in which the chip 10 is provided with the receiving groove 11, and the molten solder assemblies 30 are filled in the receiving groove 11, so as to reduce or avoid the overflow of the molten solder assemblies 30, and reduce the risk of bridging between two adjacent solder assemblies 30.

In an implementation manner, the semiconductor assembly further includes a plurality of conductive members 40, the conductive members 40 correspond to the solder members 30 one by one, and the solder members 30 are disposed on one side of the second surface 102 through the conductive members 40. The electrical connection between two adjacent chips 10 is realized by the conductive member 40.

The conductive member 40 may be made of copper, nickel, tin, or other suitable materials, the melting point of the conductive member 40 is higher than that of the solder member 30, and at a predetermined temperature, the solder member 30 is in a molten state, and the shape of the conductive member 40 remains unchanged.

In the specific embodiment, the chip 10 is further provided with a through hole 12, the through hole 12 may be a linear type or a curved type, one end of the through hole 12 is communicated with the accommodating groove 11, and the other end is located on the second surface 102 of the chip 10. At least a portion of the conductive element 40 is disposed in the through hole 12, i.e., the conductive element 40 is shaped to match the through hole 12, so that the conductive element 40 can be inserted into the through hole 12. The welding part 30 is arranged on one side of the second surface 102 through the conducting part 40, if the lower end part of the conducting part 40 is flush with the second surface 102, the welding part 30 is connected to the lower end part of the conducting part 40, and the welding part 30 is equivalently directly connected to the second surface 102; if the lower end of the conductive member 40 protrudes from the second surface 102, the welding member 30 is connected to the lower end of the conductive member 40, and the lower end of the welding member 30 is spaced from the second surface 102.

In some embodiments, the end of the conductive member 40 connecting the solder member 30 protrudes from the through hole 12 corresponding to the conductive member 40.

It should be noted that, one receiving groove 11 corresponds to one welding member 30 and one conducting member 40, and the lower end portion of the conducting member 40 (the end portion of the conducting member 40 connected to the welding member 30) protrudes from the opening of the through hole 12 on the second surface 102, i.e. the lower end portion of the conducting member 40 (the end portion of the conducting member 40 connected to the welding member 30) is spaced apart from the second surface 102 by a distance d 1. The through hole 12 is a through hole 12 connected to the conductive member 40, and is not a through hole 12 on a chip located on an upper layer (lower layer) of the conductive member 40.

The 2.5D/3D package has a high requirement for heat dissipation of the chip 10, and increases airflow through the distance D1, which is beneficial to heat dissipation of the chip 10.

In some embodiments, the other end of the conductive member 40 is flush with the bottom of the receiving groove 11 corresponding to the conductive member 40, so as to ensure sufficient space of the receiving groove 11, which is beneficial for the molten welding member 30 to be filled in the receiving groove 11, and prevent the molten welding member 30 from overflowing into the receiving groove 11.

The other end of the conductive member 40 is an upper end of the conductive member 40. The through hole 12 is a through hole 12 connected to the conductive member 40, and is not a through hole 12 on a chip located on an upper layer (lower layer) of the conductive member 40.

As a realizable manner, the inner wall of the receiving groove 11 is provided with the conductive layer 50, and the conductive layer 50 is connected with the conductive member 40.

The material of the conductive layer 50 is the same as that of the conductive member 40, and the conductive layer 50 is coated on the inner wall of the receiving groove 11 by a vapor deposition method. The conductive layer 50 is connected to the conductive member 40, and the arrangement of the conductive layer 50 is equivalent to increase the contact area between the conductive member 40 and the welding member 30, which is beneficial to the stable information transmission between the conductive member 40 and the welding member 30.

In an implementation manner, the solder part 30 of the upper chip is in limit fit with the accommodating groove 11 of the lower chip.

In the embodiment, the position-limiting fit is that the welding members 30 are inserted into the receiving groove 11, and a part of the welding members 30 or all of the welding members 30 are located in the receiving groove 11. Before two adjacent chips 10 are not connected, the welding part 30 is located in the containing groove 11, so that the degree of freedom of movement in the horizontal direction between the two chips 10 is restrained, and the two adjacent chips 10 are prevented from shifting.

Further, the welding part 30 of the upper chip is located in the containing groove 11 of the lower chip, and the highest point of the welding part 30 is lower than or flush with the opening of the containing groove 11, so that the welding part 30 in a molten state can be completely contained in the containing groove 11.

In an achievable manner, the accommodating groove 11 is open in a flared shape.

It should be noted that the cross section of the opening of the receiving groove 11 is larger than the cross section of the bottom of the receiving groove 11, so that the space of the receiving groove 11 is increased, and more molten weld parts 30 can be filled conveniently, and the molten weld parts 30 cannot overflow out of the receiving groove 11; in addition, the depth of the accommodating groove 11 is reduced, and the influence on the rigidity and strength of the chip 10 is avoided.

In this embodiment, the number of the receiving grooves 11 is plural, and preferably, the receiving grooves 11 are arranged at equal intervals of d2, and a gap exists between two adjacent receiving grooves, which is beneficial to avoiding bridging between two adjacent welding members 30. In some embodiments, the plurality of receiving grooves 11 may also be arranged at unequal intervals.

Fig. 3 to 8 show a schematic illustration of a method for producing a semiconductor component.

The manufacturing method of the semiconductor component comprises the following steps:

s1, providing a wafer, wherein the wafer comprises a chip layer 10a and a grinding layer 10b, a containing groove 11 is formed in the surface, opposite to the grinding layer 10b, of the chip layer 10a, and the opening of the containing groove 11 is in a flaring shape;

it should be noted that, a through-silicon-via technology is adopted to form the accommodating groove 11 on the surface of the chip layer 10a opposite to the polishing layer 10b, and the longitudinal cross section of the accommodating groove 11 is in other suitable shapes such as a triangle, a trapezoid, a semicircle or a semi-ellipse, as shown in fig. 3, the longitudinal cross section of the accommodating groove 11 is in a triangle. The thickness of the chip layer 10a is L1, the thickness of the polishing layer 10b is L2, and the depth L3 of the accommodating groove 11 is smaller than the depth L1 of the chip layer 10aL 1.

S2, the receiving cavity 11 is opened with a blind hole 12a extending toward the polishing layer 10b from the bottom thereof, the blind hole 12a penetrates through the chip layer 10a and ends at the polishing layer 10 b;

the sum of the depths of the accommodating groove 11 and the blind hole 12a is L1.

S3, laying a passivation layer 60 on the surface of the chip layer 10a, which faces away from the grinding layer 10 b;

it should be noted that a passivation layer 60 may be formed on the surface of the chip layer 10a facing away from the polishing layer 10b by a vapor deposition method, so as to protect the surface of the chip layer 10a facing away from the polishing layer 10b, and facilitate the formation of the conductive member 40 in the subsequent process.

S4, laying a conductive layer 50 on the inner wall of the containing slot 11 and forming a conductive member 40 in the blind hole 12 a;

it should be noted that the conductive layer 50 may be formed on the inner wall of the accommodating groove 11 by a vapor deposition method; a conductive member 40 is formed in the blind hole 12a, and the conductive member 40 and the conductive layer 50 are made of the same material. The conductive member 40 is connected to the conductive layer 50.

S5, polishing the polishing layer 10b until the polishing layer 10b disappears;

note that the wafer is turned upside down and polished by the polishing apparatus until the thickness L2 of the polishing layer 10b is reduced to 0.

S6, the passivation layer 60 is removed and the solder member 30 is connected to the lower end of the conductive member 40.

Note that, the passivation layer 60 is removed, the solder members 30 correspond to the conductive members 40 one by one, and the solder members 30 are connected to the lower end portions of the conductive members 40, and the chip layer 10a may be referred to as a chip 10.

Between steps S5 and S6, the length of the conductive member 40 may be extended so that the lower end of the conductive member 40 protrudes from the surface of the chip layer 10a facing the polishing layer 10 b. At this time, a distance d1 exists between the lower end of the solder 30 and the surface of the chip layer 10a facing the polishing layer 10 b.

Fig. 9 shows a schematic structural diagram of an apparatus for die bonding.

As shown in fig. 9, the apparatus for die bonding includes a carrier 70 and a number of heating mechanisms 80. The heating mechanism 80 is located below the carrier 70.

The carrier 70 is provided with a plurality of carrier areas 71, and the carrier areas 71 are at least used for fixing the substrate of the chip to be bonded; the heating mechanisms 80 are disposed on one side of the bearing member 70, and the heating mechanisms 80 correspond to the bearing areas 71 one by one. The heating mechanism 80 includes a plurality of heat conducting members 82, the heat conducting members 82 are in one-to-one correspondence with and abut against the conductive connecting wires 21 of the substrate, and the heat conducting members 82 are in heat transfer with the substrate, so that the substrate and the chip are in heat transfer, and then the electrical connection between the substrate and the chip is completed, and the substrate and the chip form a semiconductor assembly.

It should be noted that the supporting region 71 may be a groove structure, a planar structure or other suitable structures, and the supporting region 71 is used for fixing the semiconductor device or the substrate, so as to facilitate heat transfer between the semiconductor device or the substrate and the heating mechanism 80. The conductive connecting line 21 of the substrate has good electrical conductivity and good thermal conductivity, the heat conducting member 82 of the heating mechanism 80 is in partial contact with a specific part of the substrate, the heat transfer efficiency between the two parts is high, other parts of the substrate are not affected, and the substrate is prevented from warping. In addition, a plurality of heating mechanism 80 corresponds a plurality of bearing area, has improved dress efficiency.

In the related art, the reflow soldering technology is suitable for a large-size chip 10, and due to the excessively high ambient temperature provided by the reflow soldering technology, when the electrical connection between the chip 10 and the substrate 20 is realized, the chip 10 or the substrate 20 is easily warped, and further, problems of solder joint bridging, insufficient soldering and the like exist; the hot-press bonding technology can avoid the problems of solder joint bridging, insufficient solder joint and the like, but is limited by the form of a patch, and can only realize the mounting efficiency of one piece at a time.

Based on this, the present application provides an apparatus for die bonding, in which the heat conducting member 82 of the heating mechanism 80 is in heat transfer with a specific portion of the substrate, the two are in local contact, the heat transfer efficiency between the two is high, other portions of the substrate are not affected, and the warpage of the substrate is avoided. In addition, a plurality of heating mechanism 80 corresponds a plurality of bearing area, has improved dress efficiency.

As an implementation manner, the carrying region 71 is a groove, the carrying surface of the carrying member 70 is recessed into the carrying member 70, and the groove is in snap fit with the substrate (semiconductor module), so that the groove is fixedly connected with the substrate (semiconductor module) to prevent the substrate (semiconductor module) from shaking.

In a practical manner, the carrier 70 is further provided with a channel 72 communicating with the carrier region 71, and the heat-conducting member 82 is provided in the channel 72.

Referring to fig. 9, in a specific embodiment, a channel 72 is formed on the bottom of the bearing area 71, the channel 72 penetrates through the bearing member 70, and the axis of the channel 72 may be vertical, or the axis of the channel 72 may be inclined at a predetermined angle to the vertical.

The heating mechanism 80 includes a heating element 81 and a heat conducting element 82 connected to the heating element 81, the heat conducting element 82 is substantially columnar, that is, the cross-sectional diameter of the heat conducting element 82 is adapted to the cross-sectional diameter of the channel 72, the heat conducting element 82 is perpendicular to the heating element 82 or arranged at a predetermined included angle with the heating element 81, that is, when the axis of the channel 72 extends along the vertical direction, the heat conducting element 82 is perpendicular to the heating element 81, when the axis of the channel 72 extends along the vertical direction, the heat conducting element 82 is arranged at a predetermined included angle with the heating element 81, that is, the heat conducting element 82 is adapted to the channel 72, the heat conducting element 82 can penetrate through the channel 72, and the heat conducting element 82 is in contact with the conductive connecting line 21 of the substrate, so as to realize the heat conduction fit of the two elements.

One end of the heat-conducting member 82 is protruded or flush with the bottom of the load-bearing area. Referring to fig. 9, in the embodiment of the present invention, the upper end of the heat-conducting member 82 is flush with the bottom of the groove, which is beneficial to the stable contact between the upper end of the heat-conducting member 82 and the conductive connection line 21 of the substrate; or, the upper end of the heat conducting member 82 protrudes out of the bottom of the groove, which is further beneficial to the stable contact between the upper end of the heat conducting member 82 and the conductive connecting line 21 of the substrate.

As a realizable manner, the orthographic projection part of the heat conducting member 82 on the electrically conductive connecting line 21 covers the electrically conductive connecting line 21, so as to ensure that the contact area of the heat conducting member 82 and the electrically conductive connecting line 21 is large enough, which is beneficial for the heat conducting member 82 and the electrically conductive connecting line 21 of the substrate to stably abut against each other and improve the heat conduction efficiency therebetween.

As an implementable manner, the apparatus for die bonding further comprises a pressing mechanism 90 for press-fitting with the semiconductor assembly.

Referring to fig. 10 and 11, it should be noted that the semiconductor assembly includes a substrate 20 and a plurality of chips 10, the plurality of chips 10 are stacked, and the stacked chips 10 are disposed on the substrate 20. The pressing mechanism 90 is located at one side of the carrier 70, i.e., the pressing mechanism 90 is disposed above the carrying area 71; the heating mechanism 80 is located below the carrier 70. When the heating mechanism 80 is in heat-conductive engagement with the semiconductor module, the pressing mechanism 90 applies a biasing force to the stacked chips 10, and warpage of the chips 10 can be prevented.

In a specific implementation, the pressing mechanism 90 includes a pressing block 91 and a ball screw mechanism, the ball screw mechanism is disposed along a vertical direction, the ball screw mechanism includes a ball screw and a nut in sliding fit with the ball screw, and the pressing block 91 is connected to the nut. The nut slides along the length direction of the ball screw to drive the pressing block 91 to be close to or far away from the bearing piece 70, and then the pressing block 91 applies acting force to the semiconductor component. The precision of the ball screw mechanism can control the time and the size of the applied acting force. The magnitude of the applied force is 0kgf to 10 kgf.

Further, the compact 91 includes a heating module for adjusting the temperature of the compact 91. The temperature of the pressing block 91 is higher than that of the chip 10, and the pressing block 91 conducts heat to the chip 10 to raise the temperature of the chip 10, thereby shortening the operating time of the heating mechanism 80.

As an implementable manner, the apparatus for chip bonding further includes a telescopic mechanism connected to the heating mechanism 80, the telescopic mechanism driving the heating mechanism 80 to reciprocate in the vertical direction.

Referring to fig. 10, it should be noted that the telescopic mechanism is connected to the heating element 81 of the heating mechanism 80, and the telescopic mechanism drives the heating element 81 to reciprocate along the vertical direction, so as to drive the heat-conducting element 82 to reciprocate, so that the upper end portion of the heat-conducting element 82 protrudes or is hidden in the channel 72. When the heating mechanism 80 is operated, the upper end part of the heat conducting member 82 protrudes from the channel 72; after the heating mechanism 80 is operated, the upper end of the heat conducting member 82 is hidden in the channel 72; the arrangement mode is beneficial to transferring the semiconductor assembly or the substrate to the next working procedure. Telescopic machanism can be electric putter, can guarantee the application environment requirement: clean and pollution-free; in addition, the device is made compact.

Of course, in this embodiment, the chip bonding apparatus is used for bonding between the multiple layers of chips and the substrate, and in other embodiments of the present invention, the apparatus can also be used for bonding between a single layer of chips and the substrate, and the specific process is similar to the bonding of the multiple layers of chips, and will not be described in detail again.

The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.