阅读说明：本技术 减轻在制备衬底的直接接合时探测焊盘的表面损伤 (Mitigating surface damage of probe pads in preparation for direct bonding of substrates ) 是由 G·高 L·W·米卡里米 G·G·小方丹 于 2020-04-14 设计创作，主要内容包括：提供了减轻在制备衬底的直接接合时探测焊盘的表面损伤的方法。方法以及层结构在测试探测期间探测焊盘表面被破坏后,通过恢复平坦直接接合表面,制备用于直接接合处理的半导体衬底。示例性方法在被破坏的探测焊盘表面上填充一系列金属以及氧化物,并且构建电介质表面以及用于混合接合的互连件。互连件可以被连接到探测焊盘和/或衬底的其他电接触。层结构被描述用于增加所得直接接合处理的产出以及可靠性。另一处理在倒数第二金属化物层上构建探测焊盘,并且施加直接接合电介质层以及金属镶嵌处理而不增加掩模层的计数。另一示例性处理以及相关的层结构将探测焊盘凹陷到较低的金属化物层并且允许在探测焊盘上的凹腔。(Methods of mitigating surface damage of probe pads in preparing direct bonding of substrates are provided. Methods and layer structures prepare semiconductor substrates for direct bonding processing by restoring a flat direct bonding surface after the probe pad surface is damaged during test probing. The exemplary method fills a series of metals and oxides on the damaged probe pad surface and builds up the dielectric surface and interconnects for hybrid bonding. The interconnect may be connected to the probe pad and/or other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another process builds a probe pad on the penultimate metallization layer and applies a direct bond dielectric layer and a damascene process without increasing the count of the mask layer. Another exemplary process and associated layer structure recesses the probe pad to a lower metallization layer and allows for a cavity on the probe pad.)

1. A method of preparing a substrate for a direct bonding process, comprising:

receiving a substrate comprising at least one metallization layer and probing pads for testing the substrate, the probing pads having protrusions resulting from contact with a test probe;

depositing or overfilling a metal on the probe pad and on at least a portion of the protrusion, the metal in direct contact with the probe pad;

planarizing the metal on the probe pad and the protrusion into a planar surface capable of a direct bonding process or a hybrid bonding process.

2. The method of claim 1, further comprising: applying a dielectric layer on the planar surface as a material for a direct bonding process or a hybrid bonding process on the dielectric layer;

patterning the dielectric layer to make openings over electrical contacts in the at least one metallization layer;

depositing a metal into at least the opening to fabricate an interconnect at the dielectric layer for the direct bonding process; and

planarizing the metal and the dielectric layer to a flatness that enables the direct bonding process or the hybrid bonding process to be performed on the dielectric layer.

3. The method of claim 2, further comprising: patterning the dielectric layer to make an opening on the probing pad; and

depositing the metal into at least the opening to fabricate an interconnect for the direct bonding process at the dielectric layer or oxide layer, the interconnect conductively connected to the probe pad.

4. The method of claim 1, wherein the probe pad is at least partially embedded in silicon nitride (Si)₃N₄) Layers or other dielectric layers.

5. The method of claim 1, wherein depositing or overfilling the metal on the probe pad comprises: plating the metal to a vertical height of a passivation layer around the probe pad; and

wherein the step of planarizing the metal on the probe pad and the bump to a planar surface comprises: the overfill metal is polished to a flatness until the metal is removed from the field regions of the substrate.

6. The method of claim 1, wherein the probe pad comprises aluminum metal (Al) and the metal deposited on the probe pad comprises copper metal (Cu).

7. The method of claim 1, further comprising: depositing an adhesion coating, a seed coating, or a barrier coating of titanium (Ti) or another metal on at least the protrusion and the probing pad prior to the step of depositing or overfilling the metal on the probing pad.

8. The method of claim 2, wherein the step of applying the dielectric layer on the planar surface as a material for direct bonding comprises: a low temperature oxide layer is applied by plasma enhanced chemical vapor deposition (PE-CVD), a low temperature Tetraethoxysilane (TEOS) oxide is applied, or another dielectric material for direct or hybrid bonding is applied.

9. The method of claim 2, further comprising: after patterning the dielectric layer, depositing a barrier layer of Ti, Ta, TaN, TiN, TiW, or a combination comprising materials, prior to depositing the copper material or the conductive material in at least the opening.

10. A layer structure for fabricating one or more direct bonding surfaces with respect to probe pads on a substrate for a microelectronic element, the layer structure comprising:

on a first side of the substrate:

a probe pad comprising at least partially embedded in silicon nitride (Si)₃N₄) Aluminum metal (Al) or copper metal (Cu) in a layer or other dielectric material layer;

a barrier layer or an adhesion layer comprising one of Ti, Ta, TaN, TiN, or TiW, or a combination of two or more selected from the group consisting of Ti, Ta, TaN, TiN, and TiW, the barrier layer or the adhesion layer applied to at least a protrusion of the probe pad caused by contact with a test probe;

a copper region deposited directly on the layer of Ti, Ta, TaN, TiN, or TiW or the combination over the probe pad, the copper region conductively connected to the probe pad; and

a first silicon oxide layer for direct bonding, the silicon oxide layer being applied on the copper region.

11. The layer structure of claim 10, further comprising: a copper interconnect for direct bonding disposed through the first silicon oxide layer by etching the first silicon oxide layer and depositing the copper interconnect or by a damascene process, wherein the copper interconnect is conductively connected to the probe pad or an electrical contact in a metallization layer of the substrate.

12. The layer structure of claim 10 further comprising a layer of tantalum (Ta) between the copper region and the first silicon oxide layer.

13. The layer structure of claim 10, wherein the substrate comprises a High Bandwidth Memory (HBM) wafer comprising vertical Through Silicon Vias (TSVs);

the layer structure further comprises: a second silicon oxide layer between the HBM wafer and the silicon nitride layer; and

a third silicon oxide layer for direct bonding on a second side of the HBM wafer, the second side of the HBM wafer opposite the first side of the HBM wafer.

14. The layer structure of claim 13, further comprising a copper interconnect for direct bonding, the copper interconnect disposed through the third silicon oxide layer.

15. A method of preparing a semiconductor substrate for a direct bonding process, comprising:

creating a probe pad in a metallization layer of the semiconductor substrate;

depositing a dielectric layer over the probing pad after the probing pad is damaged by a test probe;

planarizing the dielectric layer;

patterning the dielectric layer to make openings over electrical contacts in the metallization layer;

plating the opening with metal to become an interconnect during the direct bonding process; and

planarizing a top surface of the metal and the dielectric layer to provide a surface having metallic and non-metallic regions for a hybrid bonding process.

16. The method of claim 15, further comprising: increasing the thickness of the metallization layer relative to the top layer of the substrate to facilitate elimination of conventional layers of the substrate that are replaced by the top layer for direct bonding.

17. A method for preparing a semiconductor wafer for direct bonding processing, comprising:

creating a probing pad on a substrate for a microelectronic element, the probing pad recessed at a penultimate metallization layer or a penultimate metallization layer of the substrate;

creating a final layer comprising at least interconnects compatible with a hybrid bonding process, the final layer forming a cavity on the probe pad;

wherein when the probe pad is created on the third last metallization layer; the penultimate metallization layer also forms a portion of the cavity on the probing pad; and

hybrid bonding the substrate including at least the interconnects to a wafer, a die, or another substrate, wherein the cavity is compatible with the direct bonding process.

18. The method of claim 17, further comprising: increasing the thickness of the penultimate metallization layer or the third penultimate metallization layer relative to the last metallization layer.

19. The method of claim 17, further comprising: depositing a liquid metal in the cavity to form electrical contact between the test probe and the corresponding probing pad without damaging the metal surface of the probing pad.

20. A layer structure for preparing a semiconductor substrate for a direct bonding process, the layer structure comprising:

a probing pad of the wafer on a penultimate metallization layer or a penultimate metallization layer of the substrate;

a final layer comprising a dielectric compatible with a direct bonding process and at least an interconnect, the final layer comprising a void to form a cavity on the probe pad on an underlying metallization layer; and

wherein the penultimate metallization layer also forms a portion of the cavity on the probe pad when the probe pad is on the penultimate metallization layer.

21. The layer structure of claim 20 wherein the dielectric and at least the interconnect are directly bonded to another wafer or die; and

wherein the cavity retains an open cavity after the interconnects are directly bonded.

22. The layer structure of claim 20 further comprising at least a trace of liquid metal in the cavity for making electrical contact between a test probe and a corresponding probing pad without damaging the metal surface of the probing pad.

23. The layer structure of claim 20, wherein the penultimate metallization layer or the penultimate metallization layer comprising the probing pad has a thicker thickness than the last layer.

Background

Test probing is typically performed on a substrate (such as a substrate of semiconductor material) as well as on dies and reconstituted panels in microelectronic elements. The test probes make physical contact with the probe pads on a given substrate. But the test probes may leave "probe imprint" and surface damage ("protrusion"), which may rise above the level of the dielectric protection layer that typically occurs around or over the probe pads. Although this occurrence may not be a problem for some types of finished substrates, wafers, and dies, in order to effectively bond the substrate to a direct bonding process of other surfaces, such as in wafer-to-wafer bonding or die-to-wafer bonding, the probing pad protrusions may destroy the flatness of the entire top surface of the substrate.

The direct bonding process includes techniques to achieve oxide-oxide direct bonding between dielectrics, and also includes techniques to achieve hybrid bonding that can bond metal interconnects together in an annealing step of the same operation that bonds dielectrics directly together.

Conventional solutions to probing pad damage include adding a sacrificial metallization layer or sacrificial probe pads to the wafer, but these solutions are awkward and expensive.

SUMMARY

The present disclosure describes methods and layer structures for mitigating surface damage of probe pads in the preparation of direct bonding of substrates (such as reconstituted panels of wafers or dies or semiconductor substrates).

An exemplary method prepares a semiconductor wafer for a direct bonding process by restoring a planar surface suitable for direct bonding after damaging a probe pad surface during test probing. The exemplary method fills the damaged probe pad surface with a series of metals and oxides and builds the dielectric surface and interconnects for hybrid bonding. Exemplary layer structures associated with the methods are described for increasing the yield and reliability of the resulting direct bonding process. Another exemplary process builds the probe pads on the penultimate metallization layer and then applies a direct bond dielectric layer and a patterning or damascene process without increasing the number of metal mask layers. Another exemplary process and associated layer structure recesses the probing pad to a lower metallization layer than the top layer conventionally used for probing pads, and a cavity formed on the probing pad that does not interfere with the direct bonding at the topmost surface. In one case, liquid metal can be used in the cavity for test probing without damaging the probe pad surface.

Exemplary processing and layer Structure

Fig. 1 shows a cross-section of an exemplary substrate, in which case a semiconductor wafer (or die) 100 will be bonded to another wafer, die, or substrate in a direct bonding process. The wafer (or die) 100 is made of a semiconductor material, such as silicon, and includes one or more metallization layers 102 and probe pads 104 for testing the wafer (or die) 100. The probe pads 104 may be aluminum metal (Al), copper (Cu), or other metal. The probe pads 104 may have protrusions 106 that contact test probes that make temporary contact during testing of the wafer (or die) 100. The protrusion 106 may rise above the top level of the surrounding dielectric, oxide, or nitride layer 108, preventing the top surface of the wafer (or die) 100 from reaching the required flatness for direct bonding to another wafer or die.

Another exemplary method deposits or overfills a layer or region of metal 110, such as copper (Cu), on the probe pad 104 and on at least a portion of the protrusion 106. The deposited metal may be overfilled 111 in a layer covering the field regions 112 of the wafer (or die) 100. In one embodiment, an adhesion coating or seed coating or barrier coating (e.g., of titanium (Ti), or Ta, or TaN, or TiN, or TiW (or combinations thereof)) may be deposited on at least one of the protrusion 106 and the probe pad 104 prior to the step of depositing or overfilling the metal 110 on the probe pad 104. A seed or barrier coating of, for example, Ti, Ta, TaN, TiN, or TiW may also cover a larger area of the field region 112 prior to the step of depositing or overfilling the metal 110 on the probe pad 104 and possibly on the field region 112, which may also have a barrier coating.

As shown in fig. 2 (continuing with fig. 1), the metal 110 deposited on the probe pad 104 and the top of the protrusion 106 are then planarized 114 by Chemical Mechanical Polishing (CMP) or other polishing or planarization step to a planar surface 116, the planar surface 116 being sufficient to meet the overall planarization specifications. The step of planarizing 114 the metal 110 and the bump 106 on the probe pad 104 to a planar surface may include: the overfilled metal 111 on the field regions 112 of the wafer or die (100) is removed or polished to flatness until the metal 110 is removed from the field regions 112.

The layer of dielectric material 118 is applied to a planar surface provided by CMP. Dielectric material layer 18 is a suitable material for direct bonding or hybrid bonding to another wafer, die, or substrate. In one embodiment, the dielectric material or oxide material 118 is a "low temperature" oxide layer using plasma chemical vapor deposition (PE-CVD), such as low temperature tetraethoxysilane (LT-TEOS), or other thermal oxide or other dielectric material suitable for direct or hybrid bonding.

An exemplary process then creates a pattern 120 in the dielectric layer 118 using damascene or other techniques such that an opening 120 is formed on the electrical contact 122, on a through-silicon via, or on other interconnects that are in contact with the underlying layer of metallization 102.

A metal 124 suitable for direct bonding is then deposited or plated in the openings 120 or in the pattern to form the interconnects. The deposit metal 124 may be prepared in various ways for the direct bonding process to occur at the topmost surface of the applied layer. In an embodiment, a barrier layer of Ti, Ta, TaN, TiN, or TiW (or a combination thereof) is deposited at least at the openings 120 or at both the openings 120 and the field regions 112 prior to depositing copper metal 124 or other metal in the openings 120 and on the field regions 122, and after the step of patterning the dielectric layer 118, both the openings 120 and the field regions 112 may have a seed layer or barrier coating applied to their surfaces.

The metal 124, as well as the dielectric layer 118 and the seed or barrier coating, when present, are then planarized using CMP or other techniques to a flatness specification suitable for a direct bond process or a hybrid bond process at the topmost surface 126.

In one exemplary embodiment, the probe pads 104 are at least partially embedded in silicon nitride (Si)₃N₄) Layers or other dielectrics. The metal 110 to be deposited, plated, or overfilled onto the probe pad 104 may be increased to a vertical height that reaches or fills the top of a passivation layer, such as a silicon nitride or silicon oxide layer 108 around the probe pad 104.

Fig. 3 illustrates various exemplary stacked structures for a substrate, such as a wafer (or die) in this example, made possible in various embodiments by employing the exemplary methods described with respect to fig. 1-2. The exemplary stacked structure enables direct bonding or hybrid bonding on one or both surfaces of a substrate, such as a wafer (or die 100) and its build-up layers. The substrate may be part of a High Bandwidth Memory (HBM) wafer (or die) 100.

The example layer structure 302 for the wafer (or die) 100 provides the metal fill 110 and the damaged probe pad 104 and subsequent planarization 303 of the metal fill 110. Dielectric layer 118 on the top and bottom of structure 302 allows for direct dielectric-to-dielectric (oxide-oxide) bonding at the bottom surface, as well as hybrid bonding of both dielectric and metal regions on the top surface of structure 302. The oxide-oxide direct bond (at the bottom surface) can be accomplished by oxide-to-oxide direct bond, such as,cards are directly engaged (e.g., Xperi, san jose, ca). The top surface provides TSV exposure, using surface treatment of both metal and dielectric regions, enabling for hybrid bonding, such as may be usedCard hybrid junction (Xperi, san jose, ca).

Layer structure 304 has all of the features of layer structure 302 above, adding interconnect metal 124 in the hybrid junction at the bottom of structure 304. In this exemplary structure 304, the interconnect metal 124 is electrically connected to the same circuit to which the probe pad 104 is also connected, thereby providing the possibility of testing the probe circuit before connecting the same circuit to another wafer, die or substrate.

Layer structure 306 has all of the features of previous layer structure 304 above with a more complete fill of interconnect metal 124 added on the bottom hybrid bonding layer. Thus, the same hybrid bonding layer that mitigates the protrusion of the damaged probe pad 104 is used for a full hybrid bonding layer having multiple interconnects. The interconnect metal 124 may be provided as a regular or irregular array, pattern, or layout including operational pads and/or non-operational "dummy" pads.

Layer structure 308 has all the features of the previous layer structure 306 with a more complete filling of interconnect metal 124 added on both the top and bottom surfaces of the structure, both the top and bottom surfaces of the structure being hybrid bonding surfaces, enabling a complete 3D wafer (or die) stack on both sides of wafer (or die) 100, by hybrid bonding on both sides.

The exemplary layer structure 302-308 may have a probe pad 104 made of aluminum metal (Al) or copper metal (Cu) on a first side of the wafer (or die) 100, the probe pad 104 being at least partially embedded in a silicon nitride layer (Si)₃N₄) In (1). A titanium (Ti) seed layer may be applied to at least the protrusion 106 of the probe pad 104, the protrusion 106 being caused by contact with a test probe. Copper regions 110 are deposited on the titanium seed layer on probe pads 104. A first silicon oxide layer 118 for direct bonding is then applied to the surface of the wafer (or die) with openings over the copper regions 110. Copper interconnects 124 for direct bonding are disposed through the silicon oxide layer 118, with at least some of the copper interconnects in contact with the copper regions 110.

A layer of tantalum (Ta) or other barrier material may also be applied between the copper region 110 and the silicon oxide layer 118. The wafer 100 may be a High Bandwidth Memory (HBM) wafer 100 including vertical Through Silicon Vias (TSVs). The structure 302-308 may have other layers such as another silicon oxide layer between the HBM wafer 100 and the silicon nitride layer, and a silicon oxide layer 118 (or other dielectric) for direct bonding or hybrid bonding on one or more surfaces of the wafer 100.

Fig. 4 illustrates other layer structures and associated exemplary methods for preparing a substrate, such as a semiconductor wafer 400 for a direct bonding process after testing the probe wafer 400 at the probe pads 104. This exemplary method eliminates the usual metallization layer, such as the conventional M4 layer, but instead creates a hybrid bonding layer to replace the eliminated conventional layer. In addition to addressing the damage of the probe pad 104, the exemplary method also results in no net increase in the number of mask layers for the wafer 400 while increasing the ability of the hybrid bond at the top surface.

In more detail, an exemplary method includes creating the probe pads 104 in a metallization layer 402, the metallization layer 402 to be located below a top layer 404, the top layer 404 for hybrid bonding to another wafer, die, or substrate. The exemplary method builds dielectric 406 of top layer 404 directly on probe pad 104, where the exemplary method associated with fig. 1-2 fills metal 110 directly on probe pad 104 rather than on dielectric 406.

After the bump 106 is caused by the test probe damaging the probe pad 104, the method deposits a dielectric layer 406, such as silicon oxide, on the probe pad 104. Dielectric layer 406 is then planarized. Next, dielectric layer 406 is patterned to form openings over electrical contacts 408 located in the underlying metallization layer 402. The openings are filled with metal 410 to form interconnects 410 that will be directly bonded during the direct hybrid bonding process.

The top surfaces of the interconnects 410 and the dielectric layer 406 are planarized to a flatness specification suitable for hybrid bonding of the metal regions 410 and the non-metal regions 406 to another wafer, to a die, or to a substrate.

In one embodiment, the thickness of the lower metallization layer 402 relative to the top layer 404 may be increased because conventional layers may be eliminated in this exemplary method.

Fig. 5 illustrates another exemplary method for preparing a semiconductor wafer for a direct bonding process, and an exemplary layer structure associated with the method. In fig. 5, a conventional structure 500 shows the probe pads 104 on the topmost metallization layer of the wafer. In contrast, the exemplary method causes the probe pads 104 to be recessed further from the top layer within the underlying layers fabricated on the wafer. The exemplary method then leaves the cavity 510 over the probe pad 104, thus nullifying the effect of any protrusion 106 generated from the probe pad 104, which may rise a sufficient vertical height to interfere with the layers above the probe pad 104, and as in the conventional structure 500, when the probe pad 104 is on top, may interfere with the direct bonding that would occur at the top layer.

The exemplary method creates the probing pad 104 on the penultimate metallization layer 502 or the third penultimate metallization layer of the wafer 504. After the successive layers are built, the method creates a final layer 506 (top-most), the final layer 506 including interconnects 508 compatible with the direct bonding process, the final layer 506 forming a cavity 510 on the probe pad 104.

When a probe pad is created on the penultimate layer 504, the penultimate metallization layer also forms part of a cavity 510 on the probe pad 104.

In one variation, an exemplary method includes: the thickness of the penultimate metallization layer 502 or the penultimate metallization layer 504, where the probing pad 104 is located, is increased relative to the subsequent layers above.

In fig. 6, when a wafer 506 including at least interconnects 508 is directly bonded to another wafer 604, die, or substrate at an interface 602, the cavity 510 is compatible with the direct bonding process, maintaining an open cavity 510 in one embodiment.

Fig. 7 illustrates an example structure that describes another example process related to the methods described with respect to fig. 5-6. In fig. 7, a liquid metal 702, such as gallium (Ga), may be placed in the cavity 510 to form electrical contact between the test probe and the corresponding probing pad 104 without damaging the metal surface of the probing pad 104. This exemplary method creates the same cavity 510 as described with respect to fig. 5-6, but uses the cavity 510 to mitigate the problem of damaged probe pads 104, albeit in a different manner. The method of fig. 5-6 allows the presence of the protrusion 106 of the probe pad 104 and the isolation of the protrusion 106 in the cavity 501, away from the direct bond interface 602. The method of fig. 7 desirably prevents damage to the probe pad 104 first, without contacting the solid surface of the probe pad 104, by making a test probe connection through the liquid metal 702.

Fig. 8 shows another process of the successive initial process steps as shown in fig. 1. As shown in fig. 1, but with reference to fig. 8, metal 110 is deposited directly on the probe pads 104 and on the protrusions 106 or at least around the protrusions 106 caused by probe damage, and the metal 110 and, if present, the tops of the protrusions 106 are subjected to a planarization process 114 by Chemical Mechanical Polishing (CMP) or other planarization or polishing step to form a planar surface 116, the planar surface 116 being sufficient to meet overall planarization specifications. The step of applying a planarization process 114 to the metal 110 and the protrusion 106 on or around the probe pad 104 to create the planar surface 116 may include: the overfill metal is removed or polished to planarity over the field areas of the wafer 100 until the metal 110 is removed from these field areas.

A layer of dielectric material 118 is then applied over the planar surface 116 provided by CMP. Dielectric material layer 118 is a suitable material for direct bonding or hybrid bonding to another wafer, die, or substrate. In one embodiment, the dielectric or oxide material is a layer of "low temperature" oxide, low temperature tetraethoxysilane (LT-TEOS) or another material suitable for direct bonding or direct hybrid bonding as known in the art.

The exemplary process then creates patterns 120 and 800 in the dielectric layer 118 using damascene or other techniques to form openings 120 and 800 over electrical contacts 122, Through Silicon Vias (TSVs), or other interconnects that are in contact with the underlying layer of metallization 102. In contrast to fig. 2, openings are also formed (or only formed) on probe pads 104 and metal 110 that has been deposited on probe pads 104 and subjected to planarization 114.

Metals 104 and 802 suitable for direct bonding are then deposited or plated in the openings 120 and 800 or in a pattern to form interconnects that will be hybrid bonded at the direct bonding interface 804. The deposited metals 124 and 802 may be prepared in various ways for a hybrid joining process to occur at the topmost surface 804 of the applied layer. In one embodiment, if the mixing of metal and semiconductor is a problem in a particular configuration, a barrier layer of Ti, Ta, TaN, TiN, or TiW (or combinations thereof) may be deposited before depositing the metals 124 and 802 (such as copper or aluminum or other materials) in the openings 120 and 800, the barrier layer being placed after patterning 120 and 800 of the dielectric layer 118.

The metals 124 and 802 and the dielectric layer 118 are then planarized using CMP or other techniques to a planarity specification that is suitable for a direct bonding process or a hybrid bonding process at the topmost surface 804.

In one exemplary embodiment, the probe pads 104 are at least partially embedded in silicon nitride (Si)₃N₄) Or other dielectric layer. The metal 110 to be deposited, plated, or overfilled onto the probe pad 104 can be increased to a vertical height that reaches or fills the top of a passivation layer, such as a silicon nitride or silicon oxide layer around the probe pad 104.

The exemplary process of fig. 8 provides a direct bond surface 804 for the hybrid bond of the oxide layer 118 and the planar metal interconnects 124 and 802, where some of the interconnects 802 are conductively connected to the underlying damaged probe pads 104 via the deposited metal 110. In one embodiment, the interconnect 802 is only on the probe pad 104, or only on the electrical contact 122 of the metallization layer 102, as shown in fig. 2.

Hybrid bonding may also occur at the planar surface 116 after planarization 114 and before placement of the dielectric layer 118 and interconnects 124 and 802. In one embodiment, the bonding surface 108 may be a plasma gas that is activated when bonding is prepared.

If the wafer 100 is a substrate made of a material suitable for hybrid bonding a dielectric or oxide material rather than a semiconductor material, then hybrid bonding may occur at the surface 116, and one or more additional metallization layers 108 and 124 and 802 may not be required.

The embodiment shown in fig. 8 is compatible with the interconnect structure and layer configuration shown in fig. 3.

Exemplary method

Fig. 9 illustrates an exemplary method 900 of preparing a wafer with probe pads for direct bonding after damaging the probe pads by filling and planarizing over the damaged probe pads, the wafer. The operations of exemplary method 900 are shown in separate blocks.

At block 902, a wafer of semiconductor material is received, including at least one metallization layer and probe pads for testing the wafer. The probing pad may have a protrusion and a surface interference contacting the test probe.

At block 904, metal is deposited on the probe pad to cover at least a portion of the protrusion.

At block 906, the metal on the probe pads and bumps is planarized to a flat surface.

At block 908, a dielectric layer is applied on the planar surface as a material for direct bonding.

At block 910, a dielectric layer is patterned to form openings over the electrical contacts in the underlying metallization layer. The openings may be made by etching, damascene processing, or even by conventional via creation.

At block 912, metal is deposited in the openings for forming interconnects during direct bonding between the wafer and another wafer, or die, or substrate to which it is directly bonded.

At block 914, the metal and dielectric layers in the openings are planarized to a flatness sufficient for direct bonding or direct hybrid bonding.

Fig. 10 illustrates an exemplary method for preparing a wafer with probing pads for direct bonding after probing pad damage by eliminating the top metallization layer of the wafer and replacing the hybrid bonding layer with the top layer of the wafer. An operational example of the exemplary method 1000 is illustrated in a separate block.

At block 1002, probe pads are created in an underlying metallization layer disposed below a top layer of a semiconductor wafer.

At block 1004, a dielectric layer is disposed on the probe pad after the probe pad is damaged by the test pad.

At block 1006, the applied dielectric layer is planarized to a flatness.

At block 1008, the dielectric layer is patterned to form openings over the electrical contacts in the underlying metallization layer.

At block 1010, the openings are plated or filled with metal to form interconnects during direct bonding.

At block 1012, the top surface of the interconnect and the dielectric layer are planarized to provide a planar surface with metallic and non-metallic regions for direct bonding (such as hybrid bonding).

Fig. 11 illustrates an exemplary embodiment of preparing a substrate, such as a wafer having probe pads for direct bonding after probe pad destruction, by recessing the probe pads in a cavity that isolates the probe pads from the direct bonding interface. The operations of exemplary method 1100 are illustrated in separate blocks.

At block 1102, probe pads are created by recessing the probe pads to a penultimate or third-to-last metallization layer of a wafer substrate for the wafer substrate being fabricated for a microelectronic element.

At block 1104, a final layer is created for the substrate, the final layer including a dielectric compatible with the direct bonding process and at least a metal interconnect, wherein the final layer has a void for forming a cavity on a probe pad disposed on an underlying metallization layer.

At block 1106, when the probe pad is created on the third last metallization layer, then the second last metallization layer also forms a portion of the cavity on the probe pad.

At block 1108, the wafer is directly bonded to another wafer, die, or substrate, including direct bonding of dielectrics and direct bonding of interconnects. The cavity is compatible with the direct bonding process and, in one embodiment, maintains an open cavity after the direct bonding process.

In the foregoing description and drawings, specific terms and reference signs have been set forth to provide a thorough understanding of embodiments of the disclosure. In some instances, terms and symbols may imply specific details that are not required to practice the embodiments. For example, any particular size, number, type of materials, manufacturing steps, etc. may be different than those described in alternative embodiments. The term "coupled" is used herein to mean directly connected as well as connected through one or more intermediate circuits or structures. The terms "example," "embodiment," and "implementation" are used to indicate an example and are not required or preferred. Furthermore, the terms "may" and "can" may be used interchangeably to refer to optional (permissible) subject matter. The absence of any term should not be construed to mean that a given feature or technique is required.

Various modifications and changes may be made to the embodiments presented herein without departing from the spirit and broader aspects of the disclosure. For example, features or aspects of any embodiment may be used in combination with any other embodiment or in place of their corresponding features or aspects. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

While the present disclosure has been presented with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover such modifications and variations as fall within the true spirit and scope of this present disclosure.

Drawings

Certain embodiments of the present disclosure will hereinafter be described with reference to the accompanying drawings, wherein like reference numerals denote like elements. It should be understood, however, that the drawings illustrate different embodiments described herein and are not meant to limit the scope of many of the techniques described herein.

Fig. 1 is an illustration of a first exemplary sequence of fabrication steps and resulting layer structures of an exemplary wafer substrate for mitigating damage to probe pads in preparing a direct bond of the wafer substrate.

Fig. 2 is a diagram of a continuation of the exemplary sequence of fabrication steps of fig. 1 and the resulting layer structure for mitigating damage to the probe pads in preparing a direct bond of the wafer substrate.

Fig. 3 is a diagram illustrating various layer structures of a wafer substrate with direct bonding enabled on one or both surfaces of the wafer substrate by the example processes shown in fig. 1-2.

Fig. 4 is a diagram of a second exemplary sequence of fabrication steps of a wafer substrate and the resulting layer structure for mitigating damage to probe pads in preparing a direct bond of the wafer substrate.

Fig. 5 is a diagram of various embodiments of a layer structure for a wafer substrate in which probing pads are built into cavities to prevent broken bumps of the probing pads from interfering with a direct bonding process at a direct bonding surface of the wafer substrate.

Fig. 6 is a diagram of the wafer substrate of fig. 5 directly bonded to another wafer substrate with the damaged probe pads isolated in the cavities that do not interfere with the direct bond interface.

Fig. 7 is an illustration of an exemplary technique for using liquid metal in a cavity built around a probe pad to form an electrical connection during probe testing while preventing damage to the solid surface of the probe pad.

Fig. 8 is a diagram of another exemplary continuation of the sequence of fabrication steps and resulting layer structures of fig. 1 for mitigating damage to a probe pad in preparation for direct bonding of a wafer substrate, wherein an interconnect or bond pad on a planar surface to be directly bonded is conductively connected to the damaged probe pad via a copper region directly contacting the damaged probe pad.

Fig. 9 is a flow chart of an exemplary method for preparing a wafer with probe pads for direct bonding after the probe pads are damaged by filling and planarizing on the damaged probe pads.

FIG. 10 is a flow chart of an exemplary method of preparing a wafer with probe pads for direct bonding after the probe pads are damaged by eliminating the top metallization layer of the wafer and replacing the direct hybrid bonding layer with the top layer of the wafer,

fig. 11 is a flow chart of an exemplary method of preparing a wafer substrate with probing pads for direct bonding after the probing pads are damaged by recessing the probing pads in cavities that isolate the probing pads from the direct bonding interface.

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