Fabrication of integrated circuits including passive electrical components

文档序号：1078456 发布日期：2020-10-16 浏览：11次中文

阅读说明：本技术 包含无源电气组件的集成电路的制造 (Fabrication of integrated circuits including passive electrical components ) 是由斯科特·沃里克克里斯蒂安·拉森埃里克·J·金约翰·L·梅兰森安东尼·S·多伊大卫于 2019-02-12 设计创作，主要内容包括：一种在衬底上制造集成电路的方法可以包括：在集成电路的非最终层中形成无源电气组件,并在集成电路的最终层中形成一个或多个电触点,使得一个或多个电触点和无源电气组件以这样的方式定位：与衬底表面垂直并且来自衬底表面的假想线与该无源电气组件和一个或多个电触点相交。(A method of fabricating an integrated circuit on a substrate may comprise: forming a passive electrical component in a non-final layer of the integrated circuit and forming one or more electrical contacts in a final layer of the integrated circuit such that the one or more electrical contacts and the passive electrical component are positioned in a manner that: perpendicular to the substrate surface and an imaginary line from the substrate surface intersects the passive electrical component and the one or more electrical contacts.)

1. A method of fabricating an integrated circuit on a substrate, comprising:

forming passive electrical components in a non-final layer of the integrated circuit; and

forming one or more electrical contacts in a final layer of the integrated circuit such that the one or more electrical contacts and the passive electrical component are positioned in a manner that: an imaginary line perpendicular to and from a surface of a substrate intersects the passive electrical component and the one or more electrical contacts.

2. The method of claim 1, wherein the passive electrical component comprises a magnetic-based component.

3. The method of claim 2, wherein the magnetic-based component comprises an inductor.

4. The method of claim 2, wherein the magnetic-based component comprises a transformer.

5. The method of claim 1, wherein the one or more electrical contacts comprise electrical bumps.

6. The method of claim 1, wherein the substrate is part of a Wafer Level Chip Scale Package (WLCSP).

7. An integrated circuit fabricated on a substrate, comprising:

a passive electrical component formed in a non-final layer of the integrated circuit; and

one or more electrical contacts formed in a final layer of the integrated circuit such that the one or more electrical contacts and the passive electrical components are positioned in a manner that: an imaginary line perpendicular to and from a surface of a substrate intersects the passive electrical component and the one or more electrical contacts.

8. The integrated circuit of claim 7, wherein the passive electrical component comprises a magnetic-based component.

9. The integrated circuit of claim 8, wherein the magnetic-based component comprises an inductor.

10. The integrated circuit of claim 8, wherein the magnetic-based component comprises a transformer.

11. The integrated circuit of claim 7, wherein the one or more electrical contacts comprise an electrical bump.

12. The integrated circuit of claim 7, wherein the substrate is part of a Wafer Level Chip Scale Package (WLCSP).

Technical Field

The present disclosure relates generally to semiconductor fabrication, and more particularly, to the fabrication and use of double-gate metal-oxide-semiconductor field effect transistors.

Background

Semiconductor device fabrication is a process used to create integrated circuits that are present in many electrical and electronic devices. This is a multi-step sequence of lithographic, mechanical and chemical processing steps during which electronic circuits are gradually created on wafers made of semiconductor material. For example, during semiconductor device fabrication, many discrete circuit components, including transistors, resistors, capacitors, inductors, and diodes, may be formed on a single semiconductor die.

Inductors are a passive circuit component that has a variety of uses. Generally, an inductor is a passive, double-ended electrical component that stores energy in a magnetic field when current flows through the inductor. Inductors formed in integrated circuits may be used for tuned circuits, inductance-based sensors, transformers, and/or other uses.

Using existing fabrication techniques, forming inductors on semiconductor surfaces has the following disadvantages: the surface area of the integrated circuit is used that may otherwise be used to place conductive material, such as bumps (bumps), to electrically couple the integrated circuit to other components external to the integrated circuit. For example, fig. 4 shows a top view of a portion of a semiconductor substrate 1 having an inductor 4 fabricated on a surface 2 of the semiconductor substrate 1, wherein the inductor 4 comprises a magnetic material 14 surrounded by a coil 10 of conductive material 8 as known in the art. As shown in fig. 4, forming inductor 4 on surface 2 uses the area of surface 2 that would otherwise be available for bumps 28 without inductor 4.

Accordingly, there is a need for techniques for forming inductors or other passive electrical components in integrated circuits while still maximizing the available surface area of the integrated circuit for placement of conductive materials.

Disclosure of Invention

In accordance with the teachings of the present disclosure, certain disadvantages and problems associated with fabricating passive electrical components in integrated circuits may be reduced or eliminated.

According to an embodiment of the present disclosure, a method of fabricating an integrated circuit on a substrate may include: forming passive electrical components in a non-final layer of the integrated circuit; and forming one or more electrical contacts in a final layer of the integrated circuit such that the one or more electrical contacts and the passive electrical components are positioned in a manner that: an imaginary line perpendicular to and from the surface of the substrate intersects the passive electrical component and the one or more electrical contacts.

In accordance with these and other embodiments of the present disclosure, an integrated circuit fabricated on a substrate may include: passive electrical components formed in non-final layers of the integrated circuit; and one or more electrical contacts formed in a final layer of the integrated circuit, such that the one or more electrical contacts and the passive electrical components are positioned in a manner that: an imaginary line perpendicular to and from the surface of the substrate intersects the passive electrical component and the one or more electrical contacts.

The technical advantages of the present disclosure will be readily apparent to one skilled in the art from the figures, descriptions, and claims included herein. The objects and advantages of the embodiments will be realized and attained by at least the elements, features, and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are explanatory examples and are not restrictive of the claims as set forth in this disclosure.

Drawings

A more complete understanding of the present embodiments and the advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

fig. 1 illustrates a side cross-sectional view of a portion of a semiconductor substrate having passive electrical components fabricated thereon, in accordance with an embodiment of the present disclosure.

Fig. 2 illustrates a top view of a portion of a semiconductor substrate having passive electrical components fabricated thereon in accordance with an embodiment of the present disclosure;

fig. 3 illustrates an isometric perspective view of a portion of a semiconductor substrate having passive electrical components fabricated thereon in accordance with an embodiment of the present disclosure;

fig. 4 shows a top view of a portion of a semiconductor substrate with passive electrical components on a surface of the semiconductor substrate as known in the art.

Detailed Description

Fig. 1 illustrates a side cross-sectional view of a portion of a semiconductor substrate 100 having passive electrical components fabricated thereon, in accordance with an embodiment of the present disclosure. Fig. 2 illustrates a top view of a portion of a semiconductor substrate 100 having passive electrical components fabricated thereon according to an embodiment of the present disclosure. Fig. 3 illustrates an isometric perspective view of a portion of a semiconductor substrate 100 having passive electrical components fabricated thereon, in accordance with an embodiment of the present disclosure. Fig. 1-3 are generally referred to herein as "the drawings".

The semiconductor substrate 100 may be formed of any suitable material including, but not limited to, silicon carbide, germanium, gallium phosphide, gallium nitride, gallium arsenide, indium phosphide, indium nitride, indium arsenide, and the like. Although not explicitly shown in the figures, many devices (e.g., transistors, resistors, etc.) may be formed in the semiconductor substrate 100 to create an integrated circuit. To provide appropriate electrical connectivity, the metallization layer 104 may be formed at appropriate locations on the surface 102 of the semiconductor substrate 100 using known techniques. Furthermore, in order to provide suitable electrical insulation, electrically insulating material 106 (e.g., a semiconductor oxide) may also be formed at suitable locations on surface 102 of semiconductor substrate 100 using known techniques.

In some cases, it may be desirable or necessary to form certain electrical components of the integrated circuit on the surface 102 of the semiconductor substrate 100. For example, it may not be feasible, or even possible, to fabricate certain devices, such as inductors or power transformers, from semiconductor materials. As described in more detail below, the figures depict forming passive electrical components, and in particular inductors, on a surface 102 of a semiconductor substrate 100.

As is known in the art, inductors are typically formed by winding a coil of conductive wire around a ferromagnetic core of magnetic material. To achieve the same effect on the semiconductor substrate 100, a first metallization layer 108, a second metallization layer 110, component vias 112, and magnetic material 114 may be formed on the surface 102 (e.g., on the electrically insulating material 106) and arranged to mimic a coil (where the first metallization layer 108, the second metallization layer 110, and the component vias 112 form a coil) wrapped around a ferromagnetic core (where the magnetic material 114 functions as a ferromagnetic core). For example, after forming the metallization layer 104 and the electrically insulating material 106 on the surface 102 and polishing/machining them to planarize the metallization layer 104 and the electrically insulating material 106, a first metallization layer 108 may be formed on the metallization layer 104 and the electrically insulating material 106 at desired locations (e.g., as shown in fig. 1, the first metallization layer 108 may be coupled to the metallization layer 104 so as to electrically couple passive electrical components formed on the surface 102 to devices formed below the surface 102). Subsequently, a first insulating layer 116 (e.g., a polymer material) may be formed over the first metallization layer 108, the metallization layer 104, and the electrically insulating material 106 to electrically insulate the first metallization layer 108 from other integrated circuit components. Then, the first insulating layer 116 may be polished/machined to planarize the first insulating layer 116. After such polishing/machining, a magnetic material 114 may be formed on the first insulating layer 116 at a desired location proximate to the first metallization layer 108 (e.g., over the first metallization layer 108 taken in a direction perpendicular to a plane defined by the surface 102), as indicated by the vertical dashed line 150 in fig. 1.

Next, a second insulating layer 118 (e.g., a polymer material) may be formed over the magnetic material 114 and the first insulating layer 116 to electrically insulate the magnetic material 114 from other integrated circuit components. The second insulating layer 118 can then be polished/machined to planarize the second insulating layer 118. After such polishing/machining, component vias 112 may be formed through the first and second insulating layers 116, 118 as needed to electrically couple the second metallization layer 110 to the first metallization layer 108 and/or the metallization layer 104. A second metallization layer 110 may then be formed on the second insulating layer 118 and the component vias 112 at desired locations (e.g., as shown in fig. 1, the second metallization layer 110 is formed proximate the magnetic material 114 and may be coupled to conductive materials such as vias 124, bump pads 126, and bumps 128) in order to electrically couple passive electrical components formed on the surface 102 to other circuits or devices within the semiconductor substrate 100 and external to the integrated circuit formed thereon.

A third insulating layer 120 (e.g., a polymer material) may then be formed on the second metallization layer 110 and the second insulating layer 118 to electrically insulate the second metallization layer 110 from other integrated circuit components. The third insulating layer 120 may then be polished/machined to planarize the second insulating layer 120. One or more additional insulating layers (e.g., a fourth insulating layer 122) may be formed over the third insulating layer 120.

To electrically couple the second metallization layer 110 to devices external to the integrated circuit formed within and on the semiconductor substrate 100, conductive vias 124 may be formed within the third insulating layer 120 and the fourth insulating layer 122, which are formed with conductive bump pads 126. Bumps 128 (e.g., solder bumps) may be formed on the bump pads 126, where the bump 128 may be one of an array of bumps 128 (e.g., in a "flip-chip" architecture) that provides an interface for conducting electricity with integrated circuits formed within and on the semiconductor substrate 100.

As also shown in the figures, other vias 130, metallization layers 132, and bump pads 134 may be formed in and/or over the various insulating layers 116, 118, 120, and 122 to provide electrical coupling of electrical components formed within the semiconductor substrate 100 to components external to the integrated circuit formed within and on the semiconductor substrate 100.

In light of the above discussion, methods and systems for fabricating integrated circuits on semiconductor substrates, and integrated circuits formed by such methods and systems, may be provided. For example, a method for fabricating an integrated circuit on a substrate (e.g., semiconductor substrate 100) may include: passive electrical components (e.g., inductors formed from the first metallization layer 108, the second metallization layer 110, the component vias 112, and the magnetic material 114) are formed in non-final layers of the integrated circuit (e.g., layers other than the fourth insulating layer 122). The method may further comprise: forming one or more electrical contacts (e.g., vias 124, bump pads 126, bumps 128) in a final layer (e.g., fourth insulating layer 122) of the integrated circuit such that the one or more electrical contacts and passive electrical components are positioned in a manner that: an imaginary line perpendicular to and from the surface of the substrate (e.g., surface 102) intersects the passive electrical component and the one or more electrical contacts. Further, the passive electrical components include magnetic-based components (e.g., including magnetic material 114). As mentioned above, such magnetic-based components may include inductors or transformers. As described above, the one or more electrical contacts include at least one of the electrical bumps (e.g., bump 128). In these and other embodiments, the semiconductor substrate 100 may be part of a Wafer Level Chip Scale Package (WLCSP).

As used herein, when two or more elements are referred to as being "coupled" to each other, the term indicates that the two or more elements are in electronic or mechanical communication (if applicable), whether indirectly connected or directly connected, with or without intervening elements.

The present disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Also, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Furthermore, an apparatus, system, or component of an apparatus or system adapted, arranged, capable, configured, realized, operable, or operated to perform a particular function recited in the claims appended hereto includes: whether the device, system or component or a particular function is activated, turned on, or unlocked, is operative, operable, or operational as long as the device, system or component is so adapted, arranged, capable, configured, implemented, operative, or operational. Thus, modifications, additions, or omissions may be made to the systems, devices, and methods described herein without departing from the scope of the disclosure. For example, components of the system and apparatus may be integrated or separated. Moreover, the operations of the systems and devices disclosed herein may be performed by more, fewer, or other components, and the methods described may include more, fewer, or other steps. Additionally, the steps may be performed in any suitable order. As used in this document, "each" refers to each member of a set or each member of a subset of a set.

Although the illustrative embodiments have been illustrated in the accompanying drawings and described below, the principles of the disclosure may be implemented using any number of techniques, whether currently known or not. The present disclosure should in no way be limited to the exemplary embodiments and techniques illustrated in the drawings and described above.

Items depicted in the figures are not necessarily drawn to scale unless specifically indicated otherwise.

All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the present disclosure and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Although the embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the disclosure.

While specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. In addition, other technical advantages will be readily apparent to one of ordinary skill in the art upon review of the foregoing figures and description.

To assist the patent office and any reader of any patent issued in relation to this application in interpreting the claims appended hereto, applicants wish to note that they are not intended to refer to 35u.s.c. § 112(f) by any appended claims or claim elements unless the word "means for … …" or "step for … …" is explicitly used in a particular claim.

The claims (modification according to treaty clause 19)