阅读说明：本技术 防分层mim电容及其制作方法 (Anti-layering MIM capacitor and manufacturing method thereof ) 是由 牛忠彩 杨宏旭 刘俊文 于 2020-07-01 设计创作，主要内容包括：本申请设计半导体制造技术领域,具体涉及一种防分层MIM电容及其制作方法。防分层MIM电容包括：第一导电层设于半导体器件上,形成MIM电容的下极板；第二导电层设于MIM电容区域位置处,形成MIM电容的上极板介质层设于MIM电容区域位置处,包括位于中间的中间氮化硅介质薄膜层,和,位于中间氮化硅介质薄膜层上、下两侧的上层氧化薄膜层和下层氧化薄膜层；上层氧化薄膜层的上表面与第二导电层的下表面接触,下层氧化薄膜层的下表面和第一导电层的上表面接触。本申请能够在保留氮化硅介质薄膜层较高的热稳定性和化学稳定性的同时,解决氮化硅介质薄膜层具有较大应力的问题,使得介质层具有良好的界面特性,避免膜层出现分层隆起的问题。(The application relates to the technical field of semiconductor manufacturing, in particular to an anti-layering MIM capacitor and a manufacturing method thereof. The anti-delamination MIM capacitor includes: the first conducting layer is arranged on the semiconductor device to form a lower electrode plate of the MIM capacitor; the second conducting layer is arranged at the position of the MIM capacitor region, and an upper electrode plate dielectric layer forming the MIM capacitor is arranged at the position of the MIM capacitor region and comprises a middle silicon nitride dielectric thin film layer positioned in the middle, and an upper oxide thin film layer and a lower oxide thin film layer positioned on the upper side and the lower side of the middle silicon nitride dielectric thin film layer; the upper surface of the upper oxide film layer is in contact with the lower surface of the second conductive layer, and the lower surface of the lower oxide film layer is in contact with the upper surface of the first conductive layer. The silicon nitride dielectric thin film layer can be kept at high thermal stability and chemical stability, and meanwhile the problem that the silicon nitride dielectric thin film layer has high stress is solved, so that the dielectric layer has good interfacial characteristics, and the problem that the film layer is layered and raised is avoided.)

1. An anti-delamination MIM capacitor comprising: the first conducting layer, the dielectric layer and the second conducting layer are sequentially stacked from bottom to top;

the first conducting layer is arranged on the semiconductor device to form a lower electrode plate of the MIM capacitor;

the second conductive layer is arranged at the position of the MIM capacitor region to form an upper plate of the MIM capacitor

The dielectric layer is arranged at the position of the MIM capacitor area and comprises a middle silicon nitride dielectric thin film layer positioned in the middle, and an upper oxide thin film layer and a lower oxide thin film layer which are positioned on the upper side and the lower side of the middle silicon nitride dielectric thin film layer; the upper surface of the upper oxide film layer is in contact with the lower surface of the second conductive layer, and the lower surface of the lower oxide film layer is in contact with the upper surface of the first conductive layer.

2. The anti-delamination MIM capacitor according to claim 1 wherein the thickness of the middle silicon nitride dielectric thin film layer is between 10A and 1000A.

3. The anti-delamination MIM capacitor according to claim 1 wherein the material of the upper and lower oxide film layers is silicon dioxide.

4. The anti-delamination MIM capacitor according to claim 1 wherein the upper and lower oxide film layers have a thickness of 10A to 100A.

5. A manufacturing method of an anti-delamination MIM capacitor is characterized by comprising the following steps:

providing a semiconductor device, and manufacturing a first conductive layer on the semiconductor device;

depositing a lower oxide film layer, a middle silicon nitride dielectric film layer and an upper oxide film layer on the first conducting layer in sequence;

manufacturing a second conductive layer on the upper oxide film layer;

defining an MIM capacitor area pattern on the second conductive layer through photoresist;

and etching the second conductive layer according to the MIM capacitor region pattern to form an upper electrode plate of the MIM capacitor.

6. The method of claim 5, wherein the step of sequentially depositing a lower oxide film layer, an intermediate silicon nitride dielectric film layer, and an upper oxide film layer over the first conductive layer comprises:

and depositing a lower oxide film layer, a middle silicon nitride medium film layer and an upper oxide film layer on the first conducting layer in sequence by adopting a chemical vapor deposition process.

7. The method of fabricating an anti-delamination MIM capacitor of claim 5,

growing at a growth rate of 140A/min-180A/min to obtain a material with a refractive index of 1.45-1.53, a thickness of 10-100A and a stress of 0.8 × 10⁸Pa～5×10⁸A lower oxide film layer and an upper oxide film layer of Pa.

8. The method of claim 5, wherein the refraction is grown at a growth rate of 70A/min to 100A/minA ratio of 1.99 to 2.10, a thickness of 10 to 1000A, and a stress of 1 × 10⁹Pa～3×10⁹Pa of intermediate silicon nitride dielectric film layer.

Technical Field

The application relates to the technical field of semiconductor manufacturing, in particular to an anti-layering MIM capacitor and a manufacturing method thereof.

Background

With the development of very large scale integrated circuits, the demand for capacitance density per unit area is increasing. MIM capacitors are a key tool in order to ensure a high level of performance of the device while creating a high precision capacitance. The MIM capacitor is generally a sandwich structure, and includes a metal electrode on an upper layer and a metal electrode on a lower layer, wherein a dielectric layer is isolated between the upper metal electrode and the lower metal electrode.

In the related art, particularly, the back-end copper interconnection process usually requires multilayer stacking, and since the metal electrode film of the MIM capacitor is in direct contact with the dielectric layer, the problem of delamination or bulging of the metal electrode film is likely to occur in the case where the metal electrode film and the dielectric layer are not stress-matched. Especially for the film with larger stress, the reliability of the time Dependent point mechanism breakdown tddb (time Dependent Dielectric breakdown) of the anti-delamination MIM capacitor also faces a larger problem.

Disclosure of Invention

The application provides an anti-layering MIM capacitor and a manufacturing method thereof, which can solve the problem that a film layer in the related technology is layered and raised.

As a first aspect of the present application, there is provided an anti-delamination MIM capacitor comprising: the first conducting layer, the dielectric layer and the second conducting layer are sequentially stacked from bottom to top;

the first conducting layer is arranged on the semiconductor device to form a lower electrode plate of the MIM capacitor;

the second conductive layer is arranged at the position of the MIM capacitor region to form an upper plate of the MIM capacitor

The dielectric layer is arranged at the position of the MIM capacitor area and comprises a middle silicon nitride dielectric thin film layer positioned in the middle, and an upper oxide thin film layer and a lower oxide thin film layer which are positioned on the upper side and the lower side of the middle silicon nitride dielectric thin film layer; the upper surface of the upper oxide film layer is in contact with the lower surface of the second conductive layer, and the lower surface of the lower oxide film layer is in contact with the upper surface of the first conductive layer.

Optionally, the thickness of the middle silicon nitride dielectric thin film layer is 10A-1000A.

Optionally, the material of the upper oxide film layer and the material of the lower oxide film layer both adopt silicon dioxide.

Optionally, the thickness of the upper oxide film layer and the lower oxide film layer is 10A to 100A.

As a second aspect of the present application, there is provided a method for manufacturing an anti-delamination MIM capacitor, the method comprising:

providing a semiconductor device, and manufacturing a first conductive layer on the semiconductor device;

depositing a lower oxide film layer, a middle silicon nitride dielectric film layer and an upper oxide film layer on the first conducting layer in sequence;

manufacturing a second conductive layer on the upper oxide film layer;

defining an MIM capacitor area pattern on the second conductive layer through photoresist;

and etching the second conductive layer according to the MIM capacitor region pattern to form an upper electrode plate of the MIM capacitor.

Optionally, the step of depositing a lower oxide film layer, a middle silicon nitride dielectric film layer, and an upper oxide film layer on the first conductive layer in sequence includes:

and depositing a lower oxide film layer, a middle silicon nitride medium film layer and an upper oxide film layer on the first conducting layer in sequence by adopting a chemical vapor deposition process.

Optionally, the growth rate of 140A/min-180A/min is used for growing the material with the refractive index of 1.45-1.53, the thickness of 10A-100A and the stress of 0.8 × 10⁸Pa～5×10⁸A lower oxide film layer and an upper oxide film layer of Pa.

Optionally, the growth rate of 70A/min-100A/min is used for growing the material with the refractive index of 1.99-2.10, the thickness of 10A-1000A and the stress of 1 × 10⁹Pa～3×10⁹Pa of intermediate silicon nitride dielectric film layer.

The technical scheme at least comprises the following advantages: the silicon nitride dielectric thin film layer is formed on the interface of the silicon nitride dielectric thin film layer in direct contact with other layers, the second conducting layer is manufactured on the upper oxide thin film layer, the oxide thin film layer has a blocking effect on the transmission of the stress of the silicon nitride dielectric thin film layer, and the transmission of the stress of the silicon nitride dielectric thin film layer to the interface of the oxide thin film layer can be reduced, so that the problem that the silicon nitride dielectric thin film layer has large stress can be solved while the high thermal stability and chemical stability of the silicon nitride dielectric thin film layer are kept, the dielectric layer has good interface characteristics, and the problem that the film layer is layered and protruded is avoided.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic diagram of an anti-delamination MIM capacitor structure according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of an anti-delamination MIM capacitor structure with copper interconnection structure fabricated on the basis of FIG. 1;

fig. 3 is a flowchart of a method for fabricating an anti-delamination MIM capacitor according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

Fig. 1 is a diagram of an anti-delamination MIM capacitor structure according to an embodiment of the present application, where the anti-delamination MIM capacitor structure includes: the first conducting layer, the dielectric layer and the second conducting layer are sequentially stacked from bottom to top.

The first conductive layer 110 is arranged on the semiconductor device to form a lower electrode plate of the MIM capacitor;

the second conductive layer 120 is disposed at the position of the MIM capacitor region to form the upper plate of the MIM capacitor

The dielectric layer 130 is arranged at the position of the MIM capacitor region and comprises a middle silicon nitride dielectric thin film layer 131 positioned in the middle, and an upper oxide thin film layer 132 and a lower oxide thin film layer 133 positioned on the upper side and the lower side of the middle silicon nitride dielectric thin film layer; the upper surface of the upper oxide film layer 132 is in contact with the lower surface of the second conductive layer 120, and the lower surface of the lower oxide film layer 133 is in contact with the upper surface of the first conductive layer 110.

Fig. 2 shows a copper interconnect structure fabricated on the basis of the MIM capacitor structure shown in fig. 1, and includes, as shown in fig. 2, an interconnect layer 210 covering the periphery of the MIM capacitor structure shown in fig. 1, in which a plurality of copper interconnect lines 220 are formed, a portion of the copper interconnect lines 220 being in downward contact with the upper surface of the first conductive layer 110, and a portion of the copper interconnect lines 220 being in downward contact with the upper surface of the second conductive layer 120.

Because the intermediate silicon nitride dielectric film layer contains large internal stress, the interface of the intermediate silicon nitride dielectric film layer directly contacted with other layers generates the problem of delamination or uplift in the process of heat treatment and subsequent processes. Form the oxide film layer on the interface of silicon nitride dielectric thin film layer and other layer direct contact, because the oxide film layer has to block the cushioning effect to the transmission of silicon nitride dielectric thin film layer stress, can reduce silicon nitride dielectric thin film layer stress and transmit to the interface of oxide film layer, thereby can be when keeping higher thermal stability and the chemical stability of silicon nitride dielectric thin film layer, solve the problem that silicon nitride dielectric thin film layer has great stress, make the dielectric layer have good interfacial characteristic, avoid the problem that the layering uplift appears in the rete.

Wherein the intermediate silicon nitride dielectric thin film layer is formed by adopting a chemical vapor deposition technology and growing at a growth rate of 70-100A/min, the refractive index of the intermediate silicon nitride dielectric thin film layer is 1.99-2.10, the thickness of the intermediate silicon nitride dielectric thin film layer is 10-1000A, and the stress of the intermediate silicon nitride dielectric thin film layer is 1 × 10⁹Pa～3×10⁹Pa。

The upper oxide film layer and the lower oxide film layer are made of silicon dioxide, the silicon dioxide is formed by adopting a chemical vapor deposition technology in a reaction cavity and growing at a growth rate of 140A/min-180A/min, the refractive index of the silicon dioxide is 1.45-1.53, the thickness of the silicon dioxide is 10A-100A, and the stress of the silicon dioxide is 0.8 × 10⁸Pa～5×10⁸Pa。

Fig. 3 is a manufacturing method of an anti-delamination MIM capacitor according to an embodiment of the present disclosure, and as shown in fig. 3, the manufacturing method of the anti-delamination MIM capacitor includes the following steps:

step S310, providing a semiconductor device, and fabricating a first conductive layer on the semiconductor device.

The first conductive layer is used as a lower plate of the MIM capacitor, and the material of the first conductive layer can be metal, ITO, or other conductive materials.

Step S320, depositing a lower oxide film layer, a middle silicon nitride dielectric film layer and an upper oxide film layer on the first conductive layer in sequence.

Wherein, the materials of the lower oxide film layer and the upper oxide film layer are both silicon dioxide, the silicon dioxide is formed by adopting a chemical vapor deposition technology in a reaction cavity and growing at a growth rate of 140A/min-180A/min, the refractive index of the silicon dioxide is 1.45-1.53, the thickness is 10A-100A, and the stress is 0.8 × 10⁸Pa～5×10⁸Pa。

The intermediate silicon nitride dielectric film layer is grown by adopting a chemical vapor deposition technology at a growth rate of 70-100A/min, the refractive index of the intermediate silicon nitride dielectric film layer is 1.99-2.10, the thickness of the intermediate silicon nitride dielectric film layer is 10A-1000A, and the stress of the intermediate silicon nitride dielectric film layer is 1 × 10⁹Pa～3×10⁹Pa。

Step S330, a second conductive layer is formed on the upper oxide film layer.

The second conductive layer is used as an upper plate of the MIM capacitor, and the material of the second conductive layer can be metal, ITO, or other conductive materials.

Step S340, defining a MIM capacitor region pattern on the second conductive layer by using a photoresist.

And step S350, etching the second conducting layer according to the MIM capacitor region pattern to form an upper electrode plate of the MIM capacitor.

In the process of etching the upper electrode plate of the MIM capacitor, the upper oxide film layer positioned between the second conductive layer and the middle silicon nitride dielectric film layer can improve the control quantity of the etching process, and the reliability of the finally formed MIM capacitor is improved by avoiding excessive etching.

The method for manufacturing the anti-layering MIM capacitor provided by the embodiment of the application has the advantages that by manufacturing the first conducting layer on the semiconductor device, a lower oxide film layer, a middle silicon nitride dielectric film layer and an upper oxide film layer are deposited on the first conducting layer in sequence, forming a silicon nitride dielectric film layer on the surface of the substrate, forming an oxide film layer on the interface of the silicon nitride dielectric film layer directly contacting with other layers, manufacturing a second conductive layer on the upper oxide film layer, because the oxidation film layer has the function of blocking the transmission of the stress of the silicon nitride dielectric film layer, the transmission of the stress of the silicon nitride dielectric film layer to the interface of the oxidation film layer can be reduced, thereby retaining higher thermal stability and chemical stability of the silicon nitride dielectric film layer, the problem that a silicon nitride dielectric film layer has large stress is solved, so that the dielectric layer has good interface characteristics, and the problem that the film layer is layered and raised is avoided.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.