阅读说明：本技术 利用电网/接地网结构上的管芯上槽线的隔离增强 (Isolation enhancement using on-die slot lines on grid/ground grid structures ) 是由 Z·D·吴 P·厄帕德亚亚 K-Y·常 于 2018-12-14 设计创作，主要内容包括：本文的示例描述了用于将包括敏感部件(例如,电感器或电容器)的IC(100)的部分与接地平面(415)中的返回电流(330)隔离的技术。由IC中的发射器(105)或驱动器生成的输出电流会生成磁场(405),磁场(405)在接地平面中感应出返回电流。如果返回电流接近敏感部件(305),则返回电流会注入噪声,这会对IC中的其它部件产生负面影响。为了将敏感部件与返回电流隔离,本文的实施例包括形成穿过接地结构的槽(500),接地结构包括在敏感部件的一个或多个侧上的接地平面。(Examples herein describe techniques for isolating portions of an IC (100) that include sensitive components (e.g., inductors or capacitors) from return currents (330) in a ground plane (415). An output current generated by a transmitter (105) or driver in the IC generates a magnetic field (405), and the magnetic field (405) induces a return current in the ground plane. If the return current is close to the sensitive component (305), the return current may inject noise, which may negatively affect other components in the IC. To isolate the sensitive component from return currents, embodiments herein include forming a slot (500) through a ground structure that includes a ground plane on one or more sides of the sensitive component.)

1. An integrated circuit, comprising:

a ground structure;

a source;

a transmitter, wherein when the transmitter is active, a return current flows from the source through the ground structure to the transmitter;

a passive component disposed between the source and the transmitter;

a first slot extending through the ground structure, wherein the first slot is between the passive component and the source; and

a second slot extending through the ground structure, wherein the second slot is between the passive component and the emitter, wherein the respective first ends of the first and second slots terminate at an edge of the ground structure.

2. The integrated circuit of claim 1, wherein respective second ends of the first and second slots terminate within the ground structure such that the return current can flow around the respective second ends but is prevented from flowing around the respective first ends.

3. The integrated circuit of claim 1 or claim 2, further comprising:

a semiconductor substrate, wherein the ground structure comprises a plurality of metal routing layers disposed on the semiconductor substrate, wherein the first and second slots extend through the plurality of metal routing layers.

4. The integrated circuit of claim 3, wherein the passive component is disposed over the plurality of metal routing layers.

5. The integrated circuit of claim 4, wherein the passive component comprises at least one of an inductor and a capacitor.

6. The integrated circuit of any of claims 1-5, wherein the return current is generated at the source by a magnetic field induced using the transmitter drive signal.

7. The integrated circuit of any of claims 1-6, further comprising:

a phase locked loop comprising the passive component; and

a second transmitter configured to receive a control signal from the phase locked loop when driving a signal.

8. An integrated circuit, comprising:

a ground structure;

a source;

a sink, wherein a return current flows through the ground structure from the source to the sink;

an inductor disposed between the source and the sink; and

a first slot extending through the ground structure, wherein the first slot is between the inductor and the source, wherein a first end of the first slot terminates at an edge of the ground structure.

9. The integrated circuit of claim 8, further comprising:

a second slot extending through the ground structure, wherein the second slot is between the inductor and the sink, wherein a first end of the second slot terminates at the edge of the ground structure.

10. The integrated circuit of claim 9, wherein respective second ends of the first and second slots terminate within the ground structure such that the return current can flow around the respective second ends, wherein the return current is prevented from flowing around the first ends of the first and second slots.

11. The integrated circuit of any of claims 8-10, further comprising:

a transmitter comprising the sink, wherein the return current is generated at the source by a magnetic field induced using the transmitter drive signal.

12. The integrated circuit of any of claims 8-11, further comprising:

a semiconductor substrate, wherein the ground structure comprises a plurality of metal routing layers disposed on the semiconductor substrate, wherein the first slot extends through the plurality of metal routing layers.

13. The integrated circuit of claim 12, wherein the inductor is disposed over the plurality of metal routing layers.

14. A method of fabricating an integrated circuit, the method comprising:

forming an active device in an active region of a semiconductor substrate;

forming a ground structure over the active region of the semiconductor substrate;

forming a first slot and a second slot through the ground structure; and

forming a passive component over the ground structure and between the first and second troughs, wherein the respective first ends of the first and second troughs terminate at an edge of the ground structure.

15. The method of claim 14, wherein the respective second ends of the first and second slots terminate within the ground structure such that the return current can flow around the respective second ends but is prevented from flowing around the respective first ends.

Technical Field

Examples of the present disclosure generally relate to isolating passive components in an Integrated Circuit (IC) using slots.

Background

Transmitters and other drive circuits in the IC may output signals, thereby generating a large amount of return current in the ground plane. In other words, the transmitter generates a current for driving (e.g., a clock or power network), which in turn generates a magnetic field that induces a return current. Typically, the return current flows to a sink in the transmitter. However, when designing an IC, it is difficult to control and predict the direction and source of the return current. If a significant amount of return current flows near a passive component (e.g., an inductor or capacitor) in or on the IC, the return current may inject noise that may affect the function of other devices in the IC that contain the passive component (e.g., an oscillator or a phase-locked loop). Therefore, being able to isolate the passive components from the return current may improve the functionality of the IC.

Disclosure of Invention

Techniques for operating and fabricating integrated circuits are described. One example is an integrated circuit that includes a ground structure, a source, and a transmitter, wherein when the transmitter is active, a return current flows from the source through the ground structure to the transmitter. The integrated circuit further comprises: a passive component disposed between the source and the emitter; a first slot extending through the ground structure, wherein the first slot is between the passive component and the source; and a second slot extending through the ground structure, wherein the second slot is between the passive component and the emitter, wherein the respective first ends of the first and second slots terminate at an edge of the ground structure.

In some embodiments, the respective second ends of the first and second slots may terminate within the ground structure such that return current may flow around the respective second ends but is prevented from flowing around the respective first ends.

In some embodiments, the integrated circuit may further include a semiconductor substrate. The ground structure may include a plurality of metal wiring layers disposed on the semiconductor substrate. The first and second slots may extend through the plurality of metal routing layers.

In some embodiments, passive components are disposed over multiple metal routing layers.

In some embodiments, the passive component may include at least one of an inductor and a capacitor.

In some embodiments, the return current may be generated at the source by a magnetic field induced using the transmitter drive signal.

In some embodiments, the integrated circuit may further include a phase-locked loop having passive components and a second transmitter configured to receive a control signal from the phase-locked loop when driving the signal.

One example described herein is an integrated circuit that includes a ground structure, a source, and a sink, where a return current flows from the source through the ground structure to the sink. The integrated circuit further includes an inductor disposed between the source and the sink; and a first slot extending through the ground structure, wherein the first slot is between the inductor and the source, and a first end of the first slot terminates at an edge of the ground structure.

In some embodiments, the integrated circuit may further include a second slot extending through the ground structure. The second slot may be between the inductor and the sink. The first end of the second slot may terminate at an edge of the ground structure.

In some embodiments, the respective second ends of the first and second slots may terminate within the ground structure such that a return current may flow around the respective second ends. The return current may be prevented from flowing around the first ends of the first and second slots.

In some embodiments, the integrated circuit may further comprise a transmitter having a sink. The return current may be generated at the source by a magnetic field induced using the transmitter drive signal.

In some embodiments, the integrated circuit may further include a semiconductor substrate. The ground structure may include a plurality of metal wiring layers disposed on the semiconductor substrate. The first slot may extend through the plurality of metal routing layers.

In some embodiments, the inductor may be disposed over a plurality of metal routing layers.

An example described herein is a method, comprising: forming an active device in an active region of a semiconductor substrate; forming a ground structure over an active region of a semiconductor substrate; cutting through the first and second slots of the ground structure; and forming a passive component over the ground structure and between the first and second troughs, wherein the respective first ends of the first and second troughs terminate at an edge of the ground structure.

In some embodiments, the respective second ends of the first and second slots may terminate within the ground structure such that return current may flow around the respective second ends but is prevented from flowing around the respective first ends.

In some embodiments, the method may further comprise forming a source of return current flowing in the ground structure and forming a sink of return current flowing in the ground structure. The first slot may be between the passive component and the source, and the second slot may be between the passive component and the sink.

In some embodiments, the method may further include forming an emitter including a sink and at least one active device in the active region of the semiconductor substrate. A return current may be generated at the source by using a magnetic field induced by the transmitter drive signal.

In some embodiments, forming the ground structure may include forming a plurality of metal wiring layers separated by dielectric material over an active region of a semiconductor substrate.

In some embodiments, the first and second trenches may extend through the plurality of metal wiring layers, thereby exposing the active region of the semiconductor substrate.

In some embodiments, the respective first ends of the first and second troughs may terminate at an edge of the plurality of metal routing layers.

Drawings

So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope.

Fig. 1 is a block diagram of an integrated circuit according to an example.

Fig. 2 is a graph illustrating the effect of return current on jitter according to an example.

Fig. 3 is an integrated circuit with a return current affecting a passive component according to an example.

Fig. 4 illustrates the use of a slot with two shorted ends to block return current according to an example.

Fig. 5 is a ground structure with two slots for isolating passive components from return current according to an example.

Fig. 6 shows a top view of the grounding structure in fig. 5 according to an example.

Fig. 7 is a cross-sectional view of a slot in the grounding structure of fig. 6 according to an example.

Fig. 8 is a graph illustrating the effect of a slot on transimpedance according to an example.

Fig. 9 is a flow diagram for fabricating a slot in a ground structure to isolate a passive component from return current according to an example.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples.

Detailed Description

Various features are described below with reference to the drawings. It should be noted that the figures may or may not be drawn to scale and that elements of similar structure or function are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. They are not intended as an exhaustive description of the specification or as a limitation on the scope of the claims. Moreover, the illustrated examples need not have all of the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example, and may be practiced in any other example even if not so shown or not explicitly described.

Examples herein describe techniques for isolating an IC portion that includes a sensitive component (e.g., an inductor or a capacitor) from return currents in a ground plane. As described above, the output current generated by a transmitter or driver in the IC may generate a magnetic field, which in turn induces a return current in the ground plane. If the return current is close to the sensitive component, the return current may inject noise, which may negatively affect other devices in the IC. To isolate the sensitive component from return currents, embodiments herein include forming a slot through a ground structure that includes a ground plane on one or more sides of the sensitive component.

In one embodiment, each slot has an open first end and a shorted second end. The open end may extend to an edge of the ground structure such that return current flowing through the ground structure cannot flow around the open end. For example, the open end of the slot may terminate at the outermost edge of the ground structure, such that there is no conductive path in the ground plane surrounding the open end. Instead, the short-circuited end terminates within the ground structure so that return current can flow around that end of the slot. In one embodiment, the sensitive part is arranged between two parallel slots, such that in the absence of a slot, any return current flowing near the sensitive part is forced to instead flow around the short-circuited end of the slot, thereby mitigating the effect of the return current on the part.

Fig. 1 is a block diagram of an IC 100 according to an example. The IC 100 includes four Transmitters (TX)105 and two Phase Locked Loops (PLLs) 110. Although not shown, IC 100 may include many different circuit blocks and circuitry, such as processor blocks, non-programmable circuit blocks (e.g., digital signal processing blocks, memories, registers), and programmable circuit blocks (e.g., configurable logic blocks). In one embodiment, the IC 100 is a non-programmable chip (such as a processor or Application Specific IC (ASIC)). In another embodiment, the IC 100 is a programmable chip, such as a Field Programmable Gate Array (FPGA). In one embodiment, transmitter 105 provides a clock signal to a clock network, but is not so limited, and may drive a data signal, a power signal, and the like.

In one embodiment, the PLL110 provides a control signal to the transmitter 105 that sets the frequency of the clock signal output by the transmitter 105. However, the current driven by the transmitter 105 may induce a return current that may negatively affect the clock signal output by the transmitter 105. In one embodiment, the transmitter 105 may not use the closest PLL110 to generate their clock signals. That is, in some configurations, the transmitter 105 disposed on the left side of the IC 100 may use the control signal output by the PLL110B instead of the PLL 110A. The control signal generated by the PLL110B is almost noise free due to the return current as long as the transmitter closest to the PLL110B is not operating.

However, once the transmitter 105C or the transmitter 105D near the PLL110B begins outputting a signal, the associated current and its magnetic field may generate a return current that flows near the PLL 110B. These return currents may inject noise into passive components (e.g., inductors or capacitors) in the PLL 110B. In one embodiment, noise in the PLL110B causes jitter in the output signal of the transmitter 105A because it relies on the PLL110B to generate its clock signal.

Fig. 2 is a graph 200 illustrating the effect of return current on jitter in the transmitter 105A according to an example. The Y-axis of graph 200 shows the change in jitter in the output signal of transmitter 105A when other transmitters are actively transmitting output signals. The X-axis of graph 200 shows jitter at different data rates.

The triangles represent jitter at the transmitter 105A when the transmitter 105B is active, the squares represent jitter at the transmitter 105A when the transmitter 105C is active, and the diamonds represent jitter at the transmitter 105A when the transmitter 105D is active. As shown, activating emitter 105B has little change in the jitter in the output signal of emitter 105A. This may be because the transmitter 105B is far from the PLL110B, and therefore, any return current generated by activating the transmitter 105B has little effect on passive components in the PLL 110B. As a result, the incremental jitter is very small.

However, activating either transmitter 105C or 105D does change the jitter of the signal output by transmitter 105A. That is, the graph 200 shows that the transmitter 105C or 105D may generate a return current that affects the PLL110B, and thus increases jitter on the output signal of the transmitter 105A.

Fig. 3 shows return currents affecting passive components in IC 100 according to an example. In particular, fig. 3 shows a ground structure 300 in IC 100, and omits other structures (such as semiconductor substrates and other circuitry) that may be in IC 100. For simplicity, the ground structure 300 includes the transmitter 105C and PLL110B shown in fig. 1, but omits other transmitters and PLLs. However, the embodiments described below may be equally applied to transmitter 105D or transmitters 105A and 105B and their effect on PLL 110A.

When the current is driven using emitter 105C, the resulting magnetic field may generate a return current 330 at source 320. Although only one path for return current 330 is shown, there may be multiple paths for return current through ground structure 300. Typically, the return current 330 flows from various sources in the IC 100 through the ground structure 300 back to the sink 325 in the transmitter 105C.

In one embodiment, the source 320 may be a controlled collapse chip connection (i.e., a c4 solder bump), the source 320 being more affected by a magnetic field than the IC or other components in the underlying package (not shown). Thus, the current density of the return current in the path between the source 320 and the sink 325 may be greater than the current density in other regions of the ground structure 300. Because the inductor 305 and capacitor in the PLL110B are on the path of the return current 330 or near the path of the return current 330, the return current 330 may inject noise that then affects jitter in the transmitter(s) that depend on the output of the PLL 110B.

In one embodiment, inductor 305 and capacitor 315 form an LC tank circuit for a Voltage Controller Oscillator (VCO)310 in PLL 110B. The inductor 305 and/or the capacitor 315 may be coupled to the same ground plane in the ground structure 300, with a return current 330 flowing in the ground structure 300. Thus, the greater the current density of the return current 330 in the portion of the ground plane near the PLL110B, the greater the effect of the return current 330 on the operation of the inductor 305 and the capacitor 315.

The following embodiments describe different techniques for isolating sensitive components (e.g., inductor 305 and capacitor 315) in the PLL110B from the return current 330. In other words, reducing the amount of return current 330 flowing near the PLL110B in the ground plane may reduce noise in the PLL110B, thereby improving the quality of the control signal output by the PLL 110B.

Fig. 4 shows the use of a slot 400 with two short ends to block return current according to an example. Similar to fig. 3, fig. 4 shows a return current flowing in the ground plane 415 from the source 320 to the sink 325. In this figure, the return current is represented by a plurality of arrows showing the path of the return current as it flows in the ground plane 415 from the source 320 to the sink 325. In addition, fig. 4 shows a magnetic field 405 and an electric field 410 associated with the return current.

To isolate the PLL110B from return current, the slot 400 is cut through the ground plane 415, thereby forming an insulating region through which return current cannot flow. Conversely, as the return current approaches the slot 400, the arrow splits into a Y-shape, indicating that a first portion of the return current flows around the first end 420A of the slot 400 and a second portion of the return current flows around the second end 420B of the slot 400. The first and second portions of the return current then recombine before flowing to the sink 325. Of course, the arrows representing the return currents are a simplified representation of the paths that the return currents may travel in the ground plane 415. For example, some return currents may not recombine after flowing around the end 420, but travel directly in a substantially straight line to the sink 325.

In fig. 4, since the slot 400 terminates within the ground plane 415, the end 420 is referred to as a short-circuited end, thereby providing a conductive path for return current to flow around the slot 400 and then recombine on the other side of the slot 400. Instead, the open end is the end that terminates on the edge of the ground plane 415 (as shown in the following figures). Thus, the open end has no conductive path that allows return current to flow around the slot. In other words, rather than using the shorting end 420 to redirect return current around the slot 400, the open end prevents current from flowing around the slot 400.

If most of the return current flows directly to the sink 325 after flowing around the terminal 420, the slot 400 will successfully isolate the PLL110B from most of the return current. That is, the highest density of return current will be to the left and right of the PLL110B, rather than flowing through it. However, as shown, while the slot 400 redirects the return current around the end 420, most of the current recombines on the other side of the slot 400 as the return current flows to the sink 325. As such, a large portion of the return current flows in the portion of the ground plane 415 at the PLL110B or in the portion of the ground plane 415 in the vicinity of the PLL110B, causing the above-described problem. In practice, simulations indicate that the tank 400 can reduce the coupling between the PLL110B and the return current by only 10% -20%. Thus, while the slot 400 does reduce the coupling between the PLL110B and the return current, the slot structure described below may provide better results.

Fig. 5 is a ground structure 501 with two slots 500 for isolating passive components from return current according to an example. The ground structure 501 may include multiple layers (e.g., multiple metal routing layers) disposed below or above the sink 325, the PLL110B, and the source 320. In one embodiment, one or more of the layers in the ground structure 501 form a ground plane through which return current flows between the source 320 and the sink 325, which may negatively impact the inductor 305 and/or the capacitor 315 in the PLL 110B. In one embodiment, the ground structure 501 forms an on-die power grid for the IC.

In this embodiment, the PLLs 110B are isolated from the source 320 and sink 325 by respective slots 500. One of the slots 500 (i.e., slot 500B) is disposed between PLL110B and source 320, while slot 500A is between PLL110B and sink 325. In this embodiment, the slots 500 extend in parallel, but this is not required. For example, the slot 500 may extend through the ground structure 501 in different directions as long as the slot 500 is between the PLL110B and the source 320 and between the PLL110B and the sink 325.

As described above, the sink 325 may be part of a circuit (e.g., a transmitter) that drives signals in the IC. As a result, the signal causes a return current (not shown) to flow between the source 320 and the sink 325 in the ground structure 501. However, the tank 500 reduces the amount of return current flowing at the PLL110B or near the PLL110B, thereby reducing the negative impact of the return current on the inductor 305 and the capacitor 315.

In fig. 5, instead of slots 500 having two short ends, each of the slots 500 includes one short end 510 and one open end 505. As described later, the return current may flow around the short circuited end 510 in the ground structure 501, but cannot flow around the open end 505. In this way, the tank 500 forces substantially all of the return current from the source 320 to flow around the shorted end 510.

As shown, the open end 505 terminates at an edge 515 of the ground structure 501. In one embodiment, edge 515 is a plane in the IC at which the metal wiring layers forming ground structure 300 terminate. Edge 515 may be an edge of an IC; however, in fig. 5, ground structure 501 is surrounded by periphery 520 indicating that the physical dimensions of the IC may continue even if ground structure 501 is absent. For example, the ground structure 501 may be formed only on a part of the surface of a semiconductor substrate forming an IC. The material (e.g., dielectric material) at the periphery 520 may be disposed on another portion of the semiconductor substrate surrounding the portion of the substrate supporting the ground structure 501. Terminating open end 505 at edge 515 of ground structure 501 (and assuming the material in periphery 520 is non-conductive) ensures that return current can only flow around short-circuited end 510 of slot 500.

In one embodiment, the PLL110B and the sink 325 are purposefully formed in a portion of the IC near the edge 515 of the ground structure 501. In other words, when designing the IC, the designer places the location of the PLL110 near the edge 515. Thus, the length of the slot 500 depends on the distance from the PLL110B to the edge 515. For example, if the PLL110B is placed farther from the edge 515, the length of the slot 500 is increased such that the short end 510 terminates at a distance farther from the edge 515 than the distance between the edge 515 and the inductor 305 and capacitor 315.

The depth of trench 500 varies according to the thickness of ground structure 501, and the thickness of ground structure 510 may vary according to the number of metal routing layers within structure 501. In one embodiment, the depth of the trench 500 ensures that the trench 500 extends through all metal routing layers in the ground structure 501. The width of the slot 500 is sufficient to enable the slot 500 to extend through a ground structure when the IC is manufactured. For example, the width may be in the range of 5-10 microns.

Fig. 6 shows a top view of the ground structure 501 of fig. 5 according to an example. The arrows in fig. 5 illustrate different paths that the return current may take between the source 320 and the emitter 105C (e.g., sink). In general, the respective thicknesses of the arrows indicate the density of the current in the ground structure 501. As shown, the return current flows around the short end 510. Furthermore, most of the return current (e.g., maximum current density) is to the right of the inductor 305 in the PLL 110B. That is, relatively less return current flows in the portion of the ground structure 501 below the inductor 305. For example, a small amount of return current may flow around the perimeter of inductor 305. In this manner, slot 500 mitigates return currents at or near the portion of the ground plane in ground structure 501 coupled with inductor 305. In one embodiment, a hexagonal groove or cut-out hole may be engraved on the perimeter of inductor 305 or on a dividing wall at the perimeter of inductor 305 to prevent return current from flowing directly under inductor 305, although these features are not required. In one embodiment, spiral inductor 305 experiences a canceling electromagnetic induction voltage at its differential pin terminals.

Although fig. 5 and 6 illustrate the use of two slots 500, in one embodiment only one slot may be used. For example, the ground structure 501 may include only the slot 500B separating the source 320 from the inductor 305 or only the slot 500A separating the inductor 305 from the emitter 105C. This may provide better results than using no slots or using slots 400 with two short ends as shown in fig. 4. In one embodiment, using two slots 500 makes the return current symmetrical with respect to inductor 305, which would not occur if only one of slots 500 were used. For example, if only one slot 500 is used, the path controllability of the return current is poor after passing through the slot 500, which means that a large portion can pass at the inductor 305 or near the inductor 305. That is, the shorter path (e.g., the path with the least impedance) to the sink 325 is between the shorted ends 510, which means the highest current density is to the right of the inductor 305.

In one embodiment, the inductor 305 may be spaced 100-.

Fig. 7 is a cross-sectional view of a slot 500 in the ground structure 501 of fig. 6, according to an example. Specifically, FIG. 7 is a cross-sectional view taken according to line A-A shown in FIG. 6, but with source 320 omitted. In this example, the ground structure 501 includes a plurality of metal routing layers 705 between which a dielectric material may be disposed. Although not shown, the ground structure 501 may include vias extending between the metal routing layers 705 to form interconnects between the layers 705.

The ground structure 501 is disposed on a silicon substrate 715. Although silicon is depicted, the IC 100 may include any type of semiconductor material. Further, the substrate 715 may include a crystalline semiconductor, as well as other layers. For example, substrate 715 may be a silicon-on-insulator (SOI) structure. In this embodiment, the portion of the substrate 715 that contacts the ground structure 501 includes an active region 710. In one embodiment, prior to forming the ground structure 501, the active region 710 is processed (e.g., doped or etched) to form active devices 720, which active devices 720 may include transistors or other active components. In this example, the active device 720 may form part of the emitter 105C. For example, active device 720 may include a MOSFET for driving a clock signal onto a clock network. In one embodiment, the ground structure 501 includes vias that connect the metal routing layer 705 closest to the silicon substrate 715 to the active devices 720 in the active area 710.

The slot 500 extends through the ground structure 501 until the active region 710 is reached. Although not required, in one embodiment, the trench 500 may extend into the silicon substrate 715. In any case, the trench 500 provides a barrier layer that electrically insulates the metal wiring layer 705 on both sides. As such, a return current flowing in the metal wiring layer 705 on one side of the slot 500 cannot flow through the slot 500 to reach the metal wiring layer 705 on the other side. Instead, as described above, the return current flows around the short-circuited end of the slot 500.

The conductive material forming inductor 305 is disposed on a top surface 725 of IC 100. Thus, the inductor 305 may be formed after the ground structure 501 is formed on the silicon substrate 715. Further, although not shown, additional slots following the perimeter of the inductor may be formed in the ground structure 501 proximate the inductor. Further, the ground structure 501 may include one or more vias coupling the inductor 305 to a metal routing layer 705 forming a ground plane.

Fig. 8 is a graph 800 illustrating the effect of a slot on transimpedance according to an example. Curve 805 represents the voltage difference at inductor 305 that results when emitter 105C is active but no slot is present in the ground structure. Curve 810 represents the voltage difference at inductor 305 that results when emitter 105D is active but no slot is present in the ground structure. Curve 815 represents the voltage difference at inductor 305 that results when emitter 105C is active and a slot is present in the ground structure shown in fig. 5 and 6. Curve 820 represents the voltage difference at inductor 305 that results when emitter 105D is active and there is a slot in the ground structure shown in fig. 5 and 6.

Comparing curves 805 and 810 with curves 815 and 820, it is shown that the slots reduce the coupling between inductor 305 and the return current caused by emitters 105C and 105C. In this way, the overall performance of the IC may be improved since less noise is injected into inductor 305. Thus, the functionality of any downstream circuitry that relies on inductor 305 (e.g., transmitter 105A or 105B in fig. 1) is improved.

Fig. 9 is a flow diagram of a method 900 for fabricating a slot in a ground structure to isolate a passive component from return current according to an example. At block 905, an active device is formed in an active region in a semiconductor substrate. In one embodiment, the active device includes a transistor, but is not limited thereto. A number of different processing steps may be used to form the active devices. For example, the active region may be doped and etched to form the active device. Further, additional materials (such as polysilicon, dielectric materials, metals, etc.) may be deposited on or in the active region to form active devices.

At block 910, a plurality of metal routing layers are formed over the active area. For example, after forming the active devices, a plurality of metal routing layers are formed over the active devices to provide interconnections to other areas of the IC. For example, the plurality of metal routing layers may be part of a ground structure that establishes a power grid or communication network for the IC.

In one embodiment, a dielectric layer is interposed between a plurality of metal wiring layers. However, the ground structure may include a via extending through the dielectric layer interconnected with the metal wiring layer. Furthermore, additional vias may be used to connect the metal wiring layer to active devices in the active area and to connect components that may be disposed above the metal wiring layer.

At block 915, two slots are formed, the slots extending through the metal routing layer. In one embodiment, the slots are formed in parallel with the block 910 forming the plurality of metal routing layers. That is, as each metal wiring layer is formed, portions of the layer remain open to form two slots. In this way, a plurality of metal wiring layers can be formed at the same time as the formation of the two trenches. Alternatively, in another embodiment, the slots may be formed after the plurality of metal wiring layers are formed using any suitable etching technique that may remove the plurality of metal wiring layers and the dielectric layer to expose the underlying semiconductor substrate.

In one embodiment, the slot has one end (e.g., an open end) that terminates at an edge of the metal wiring layer and an opposite end (e.g., a short end) that terminates within the metal wiring layer as shown in fig. 5 and 6.

At block 920, passive components (e.g., capacitors or inductors) are formed over the metal routing layers and between the two slots. As described above, the slot can reduce the negative effects of the return current flowing through the metal wiring layer near the passive component. This may reduce noise injected into the passive components by the return current.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various examples of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module of instructions, a segment of instructions, or a portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

While the foregoing is directed to particular examples, other and further examples may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.