阅读说明：本技术 具有内埋基板的线路载板及其制作方法与芯片封装结构 (Circuit carrier plate with embedded substrate, manufacturing method thereof and chip packaging structure ) 是由 林建辰 王梓瑄 冯冠文 于 2018-09-13 设计创作，主要内容包括：本发明提供一种具有内埋基板的线路载板及其制作方法,所述线路载板包括线路结构以及内埋基板。线路结构包括第一介电层、第一图案化线路层、凹槽以及多个第一凸块。第一介电层具有彼此相对的第一表面与第二表面。第一图案化线路层内埋于第一表面。第一凸块配置于第一表面上。第一凸块与第一图案化线路层电性连接。凹槽暴露出第一介电层的一部分。内埋基板配置于凹槽内且包括多个第二凸块。本发明还提供一种芯片封装结构,包括上述具有内埋基板的线路载板。(The invention provides a circuit carrier plate with an embedded substrate and a manufacturing method thereof. The circuit structure comprises a first dielectric layer, a first patterned circuit layer, a groove and a plurality of first bumps. The first dielectric layer has a first surface and a second surface opposite to each other. The first patterned circuit layer is buried in the first surface. The first bump is disposed on the first surface. The first bump is electrically connected with the first patterned circuit layer. The recess exposes a portion of the first dielectric layer. The embedded substrate is arranged in the groove and comprises a plurality of second bumps. The invention also provides a chip packaging structure which comprises the circuit carrier plate with the embedded substrate.)

1. A circuit carrier with a buried substrate, comprising:

the circuit structure comprises a first dielectric layer, a first patterned circuit layer, a groove and a plurality of first bumps, wherein the first dielectric layer is provided with a first surface and a second surface which are opposite to each other, the first patterned circuit layer is embedded in the first surface, the plurality of first bumps are arranged on the first surface, the plurality of first bumps are electrically connected with the first patterned circuit layer, and the groove exposes a part of the first dielectric layer; and

the embedded substrate is configured in the groove and comprises a plurality of second bumps.

2. The circuit carrier of claim 1, wherein the circuit structure further comprises at least two second patterned circuit layers, at least one second dielectric layer and at least one first conductive via, the second patterned circuit layers and the second dielectric layer are sequentially stacked on the second surface of the first dielectric layer, the first conductive via penetrates the second dielectric layer, and the second patterned circuit layers are electrically connected to another second patterned circuit layer through the first conductive via.

3. The circuit carrier of claim 1, wherein the circuit structure further comprises a patterned solder mask layer disposed on at least a bottom surface of the circuit structure relatively far from the first patterned circuit layer and the first surface of the first dielectric layer, and the patterned solder mask layer covers the first dielectric layer, the first patterned circuit layer and the embedded substrate.

4. The circuit carrier of claim 3, wherein the patterned solder mask layer exposes the first bumps and the second bumps.

5. The circuit carrier of claim 1, wherein said first dielectric layer further has a third surface, said third surface is located on said portion of said first dielectric layer exposed by said recess, and said third surface is aligned with a lower surface of said first patterned circuit layer.

6. The circuit carrier with embedded substrate of claim 1, wherein the plurality of first bumps are flush with the plurality of second bumps.

7. The circuit carrier of claim 1, wherein the buried substrate further comprises at least one dielectric layer, at least one patterned conductive layer and at least one conductive via.

8. A chip package structure, comprising:

the circuit carrier with embedded substrate as claimed in any one of claims 1 to 7;

a first chip disposed on the circuit structure of the circuit carrier with an embedded substrate, wherein the first chip is electrically connected to the circuit structure through the first bumps, and the first chip is electrically connected to the embedded substrate through the second bumps; and

and the second chip is configured on the circuit structure of the circuit carrier plate with the embedded substrate, wherein the second chip is electrically connected with the circuit structure through the plurality of first bumps, and the second chip is electrically connected with the embedded substrate through the plurality of second bumps.

9. The chip package structure according to claim 8, wherein the first chip comprises a plurality of first solder balls, the second chip comprises a plurality of second solder balls, wherein the first chip is electrically connected to the first patterned circuit layer and the embedded substrate through the plurality of first solder balls, and the second chip is electrically connected to the first patterned circuit layer and the embedded substrate through the plurality of second solder balls.

10. A method for manufacturing a circuit carrier board with a buried substrate comprises the following steps:

providing a circuit structure, wherein the circuit structure comprises a first dielectric layer, a first patterned circuit layer, a groove and a plurality of first bumps, the first dielectric layer has a first surface and a second surface which are opposite to each other, the first patterned circuit layer is embedded in the first surface, the plurality of first bumps are arranged on the first surface, the plurality of first bumps are electrically connected with the first patterned circuit layer, and a part of the first dielectric layer is exposed out of the groove; and

and arranging an embedded substrate in the groove, wherein the embedded substrate comprises a plurality of second bumps.

11. The method of claim 10, wherein the step of providing the circuit structure comprises:

providing a core layer, wherein the core layer comprises a core dielectric layer, at least one release layer and at least one copper foil layer;

forming a first patterned copper layer on the copper foil layer, wherein the first patterned copper layer comprises a plurality of concave holes;

forming a nickel layer on the first patterned copper layer, wherein the nickel layer covers the first patterned copper layer and the plurality of concave holes;

forming the plurality of first bumps and the first patterned circuit layer on the nickel layer;

pressing the first dielectric layer on the first patterned circuit layer, wherein the first dielectric layer covers the first patterned circuit layer and the plurality of first bumps;

removing a portion of the core layer, the first patterned copper layer and the nickel layer to expose the plurality of first bumps and the first patterned circuit layer; and

and removing part of the first patterned circuit layer to form the groove and expose a part of the first dielectric layer.

12. The method as claimed in claim 11, wherein after the step of laminating the first dielectric layer on the first patterned circuit layer, the method further comprises:

and forming at least two second patterned circuit layers, at least one second dielectric layer and at least one first conductive through hole, wherein the second patterned circuit layers and the second dielectric layer are sequentially stacked on the second surface of the first dielectric layer, the first conductive through hole penetrates through the second dielectric layer, and the second patterned circuit layers are electrically connected with the other second patterned circuit layer through the first conductive through hole.

13. The method as claimed in claim 11, wherein the step of forming the first patterned copper layer on the copper foil layer comprises:

forming a first patterned photoresist layer on the copper foil layer;

forming a first patterned copper layer on the copper foil layer, wherein the first patterned copper layer does not cover the first patterned photoresist layer; and

removing the first patterned photoresist layer.

14. The method of claim 11, wherein the step of forming the plurality of first bumps and the first patterned circuit layer on the nickel layer comprises:

forming a second patterned photoresist layer on the nickel layer;

forming a second patterned copper layer on the nickel layer, wherein the second patterned copper layer does not cover the second patterned photoresist layer and fills the plurality of cavities of the first patterned copper layer; and

and removing the second patterned photoresist layer.

15. The method of claim 11, wherein the step of removing the core layer, the first patterned copper layer and the nickel layer comprises:

performing a plate detaching procedure to separate the release layer and the copper foil layer from each other; and

and sequentially removing the copper foil layer, the first patterned copper layer and the nickel layer in an etching mode.

16. The method as claimed in claim 10, wherein the first dielectric layer further has a third surface, the third surface is located on the portion of the first dielectric layer exposed by the recess, and the third surface is aligned with the lower surface of the first patterned circuit layer.

17. The method as claimed in claim 10, wherein the first bumps are flush with the second bumps.

18. The method as claimed in claim 10, wherein the buried substrate further comprises at least one dielectric layer, at least one patterned conductive layer and at least one conductive via.

19. The method as claimed in claim 10, further comprising, after disposing the buried substrate in the recess:

forming a patterned solder mask layer on the bottom surface of the circuit structure relatively far from the first patterned circuit layer and the first surface of the first dielectric layer, so that the patterned solder mask layer covers the first dielectric layer, the first patterned circuit layer and the embedded substrate.

20. The method as claimed in claim 19, wherein the patterned solder mask layer exposes the first bumps and the second bumps.

Technical Field

The present invention relates to a circuit carrier, a method for fabricating the same, and a chip package structure, and more particularly, to a circuit carrier with an embedded substrate, a method for fabricating the same, and a chip package structure.

Background

At present, in a package structure in which a plurality of chips are interconnected, an interposer is often used as a bridging element to connect different chips and dispose the chips on a circuit carrier. However, with the demands of consumers for miniaturization and thinning of electronic products, the size of the chip package structure is limited by disposing the interposer on the circuit carrier, and particularly, the Z-axis height of the chip package structure is limited. Therefore, how to effectively reduce the Z-axis height of the entire chip package structure is a problem to be solved in the art.

Disclosure of Invention

The invention provides a circuit carrier plate with an embedded substrate, which can be used for integrating various different chips and has thinner thickness.

The invention provides a method for manufacturing a circuit carrier plate with an embedded substrate, which can manufacture the circuit carrier plate which can integrate various different elements and has thinner thickness.

The invention provides a chip packaging structure which has a thinner packaging thickness and a smaller packaging volume.

The invention provides a circuit carrier plate with an embedded substrate. The circuit structure comprises a first dielectric layer, a first patterned circuit layer, a groove and a plurality of first bumps. The first dielectric layer has a first surface and a second surface opposite to each other. The first patterned circuit layer is buried in the first surface. The first bump is disposed on the first surface. The first bump is electrically connected with the first patterned circuit layer. The recess exposes a portion of the first dielectric layer. The embedded substrate is arranged in the groove and comprises a plurality of second bumps.

In an embodiment of the invention, the circuit structure further includes at least two second patterned circuit layers, at least one second dielectric layer, and at least one first conductive via. The second patterned circuit layer and the second dielectric layer are sequentially stacked on the second surface of the first dielectric layer. The first conductive via penetrates the second dielectric layer. The second patterned circuit layer is electrically connected with the other second patterned circuit layer through the first conductive through hole.

In an embodiment of the invention, the circuit structure further includes a patterned solder mask layer. The patterned solder mask layer is at least arranged on the bottom surface of the circuit structure relatively far away from the first patterned circuit layer and on the first surface of the first dielectric layer. The patterned solder mask layer covers the first dielectric layer, the first patterned circuit layer and the embedded substrate.

In an embodiment of the invention, the patterned solder mask exposes the first bump and the second bump.

In an embodiment of the invention, the first dielectric layer further has a third surface. The third surface is on the portion of the first dielectric layer exposed by the recess. The third surface is aligned with the lower surface of the first patterned circuit layer.

In an embodiment of the invention, the first bump is flush with the second bump.

In an embodiment of the invention, the embedded substrate further includes at least one dielectric layer, at least one patterned conductive layer, and at least one conductive via.

The chip packaging structure comprises the circuit carrier plate with the embedded substrate, a first chip and a second chip. The first chip is configured on the circuit structure of the circuit carrier plate with the embedded substrate. The first chip is electrically connected with the circuit structure through the first bump, and the first chip is electrically connected with the embedded substrate through the second bump. The second chip is configured on the circuit structure of the circuit carrier plate with the embedded substrate. And is electrically connected with the circuit structure through the second bump. The second chip is electrically connected with the circuit structure through the first bump, and the second chip is electrically connected with the embedded substrate through the second bump.

In an embodiment of the invention, the first chip includes a plurality of first solder balls, and the second chip includes a plurality of second solder balls. The first chip is electrically connected to the first patterned circuit layer and the embedded substrate through a first solder ball. The second chip is electrically connected to the first patterned circuit layer and the embedded substrate through the second solder balls.

The invention discloses a method for manufacturing a circuit carrier plate with an embedded substrate. A circuit structure is provided and includes a first dielectric layer, a first patterned circuit layer, a recess, and a plurality of first bumps. The first dielectric layer has a first surface and a second surface opposite to each other. The first patterned circuit layer is buried in the first surface. The first bump is disposed on the first surface. The first bump is electrically connected with the first patterned circuit layer. The recess exposes a portion of the first dielectric layer. And arranging the embedded substrate in the groove. The buried substrate includes a plurality of second bumps.

In an embodiment of the invention, the step of providing the circuit structure includes the following steps. A core layer is provided and includes a core dielectric layer, at least one release layer and at least one copper foil layer. A first patterned copper layer is formed on the copper foil layer, and the first patterned copper layer includes a plurality of cavities. A nickel layer is formed on the first patterned copper layer, and the nickel layer covers the first patterned copper layer and the cavity. Forming a first bump and a first patterned circuit layer on the nickel layer. And pressing the first dielectric layer on the first patterned circuit layer. The first dielectric layer covers the first patterned circuit layer and the first bump. The core layer, the first patterned copper layer and the nickel layer are removed to expose the first bump and the first patterned circuit layer. A portion of the first patterned circuit layer is removed to form a recess and expose a portion of the first dielectric layer.

In an embodiment of the invention, after the laminating the first dielectric layer on the first patterned circuit layer, the method further includes: at least two second patterned circuit layers, at least one second dielectric layer and at least one first conductive via are formed. The second patterned circuit layer and the second dielectric layer are sequentially stacked on the second surface of the first dielectric layer. The first conductive via penetrates the second dielectric layer. The second patterned circuit layer is electrically connected with the other second patterned circuit layer through the first conductive through hole.

In an embodiment of the invention, the step of forming the first patterned copper layer on the copper foil layer includes: forming a first patterned photoresist layer on the copper foil layer. And forming a first patterned copper layer on the copper foil layer, wherein the first patterned copper layer does not cover the first patterned photoresist layer. The first patterned photoresist layer is removed.

In an embodiment of the invention, the step of forming the first bump and the first patterned circuit layer on the nickel layer includes: forming a second patterned photoresist layer on the nickel layer. And forming a second patterned copper layer on the nickel layer, wherein the second patterned copper layer does not cover the second patterned photoresist layer and fills the cavity of the first patterned copper layer. Removing the second patterned photoresist layer.

In an embodiment of the invention, the step of removing the core layer, the first patterned copper layer and the nickel layer includes: and performing a plate detaching procedure to separate the release layer and the copper foil layer from each other. The copper foil layer, the first patterned copper layer and the nickel layer are removed in sequence by etching.

In an embodiment of the invention, after the disposing the buried substrate in the groove, the method further includes: a patterned solder mask layer is formed on the bottom surface of the circuit structure relatively far away from the first patterned circuit layer and on the first surface of the first dielectric layer. The patterned solder mask layer covers the first dielectric layer, the first patterned circuit layer and the embedded substrate.

In view of the above, in the circuit carrier with an embedded substrate, the manufacturing method thereof and the chip package structure of the invention, since the circuit structure includes the groove, the embedded substrate can be configured in the groove, and the first chip and the second chip can be electrically connected to the circuit structure through the first bump respectively, and the first chip and the second chip can be electrically connected to the embedded substrate through the second bump respectively. By the design, the circuit carrier plate with the embedded substrate can integrate various different chips and has thinner thickness, and the chip packaging structure has thinner packaging thickness and smaller packaging volume.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1A to fig. 1M are schematic cross-sectional views illustrating a method for manufacturing a circuit carrier with an embedded substrate according to an embodiment of the invention.

Fig. 2 is a schematic cross-sectional view illustrating a chip package structure according to an embodiment of the invention.

[ notation ] to show

10: chip packaging structure

100: circuit carrier plate with embedded substrate

110: circuit structure

111: a first dielectric layer

111 a: first surface

111 b: second surface

111 c: third surface

112 b: a first patterned circuit layer

112b 1: lower surface

113: groove

112 a: first bump

115: a second patterned circuit layer

116: a second dielectric layer

116 a: bottom surface

117: a first conductive via

118. 119: welding-proof layer

118a, 119 a: patterned solder mask

120: embedded substrate

121: second bump

122: dielectric layer

123: patterned conductive layer

124: conductive vias

125: glue layer

210: core layer

212: core dielectric layer

214a, 214 b: release layer

216a, 216 b: copper foil layer

220: a first patterned copper layer

222: concave hole

230: nickel layer

112: a second patterned copper layer

310: first chip

312: first solder ball

320: second chip

322: second solder ball

R1: the first patterned photoresist layer

R2: the second patterned photoresist layer

R3: the third patterned photoresist layer

Detailed Description

Fig. 1A to fig. 1M are schematic cross-sectional views illustrating a method for manufacturing a circuit carrier with an embedded substrate according to an embodiment of the invention. Referring to fig. 1J, in the present embodiment, a circuit structure 110 is provided.

In detail, referring to fig. 1A, a core layer 210 is provided, wherein the core layer 210 includes a core dielectric layer 212, at least one release layer 214a, 214b (schematically illustrated as 2 layers in fig. 1A), and at least one copper foil layer 216a, 216b (schematically illustrated as 2 layers in fig. 1A).

Next, referring to fig. 1B and fig. 1C, a first patterned copper layer 220 is formed on the copper foil layer 216 a. In the present embodiment, the step of forming the first patterned copper layer 220 on the copper foil layer 216a includes, for example: first, a first patterned photoresist layer R1 is formed on the copper foil layer 216a, then a first patterned copper layer 220 is formed on the copper foil layer 216a, and the first patterned copper layer 220 does not cover the first patterned photoresist layer R1, and then the first patterned photoresist layer R1 is removed to obtain the first patterned copper layer 220. At this time, the first patterned copper layer 220 is formed to include a plurality of cavities 222. It should be noted that although the present embodiment discloses the step of forming the first patterned copper layer 220 on the copper foil layer 216a, the invention is not limited thereto.

Then, referring to fig. 1D, a nickel layer 230 is formed on the first patterned copper layer 220. Wherein the nickel layer 230 completely covers the first patterned copper layer 220 and the cavity 222, and the thickness of the nickel layer 230 is uniform.

Next, referring to fig. 1E and fig. 1F, a plurality of first bumps 112a and a first patterned circuit layer 112b are formed on the nickel layer 230. In the present embodiment, the steps of forming the first bump 112a and the first patterned circuit layer 112b on the nickel layer 230 are, for example: the second patterned photoresist layer R2 is formed on the nickel layer 230, and the second patterned copper layer 112 is formed on the nickel layer 230. Wherein the second patterned copper layer 112 does not cover the second patterned photoresist layer R2, and the second patterned copper layer 112 fills the cavity 222 of the first patterned copper layer 220. Then, the second patterned photoresist layer R2 is removed to form first bumps 112a (schematically illustrated in fig. 1G as 10) and a first patterned circuit layer 112b, as shown in fig. 1G. In the present embodiment, the first bump 112a and the first patterned circuit layer 112b are integrally formed. It should be noted that although the present embodiment discloses the step of forming the first bump 112a and the first patterned circuit layer 112b on the nickel layer 230, the invention is not limited thereto.

Referring to fig. 1G, a first dielectric layer 111 is laminated on the first patterned circuit layer 112 b. The first dielectric layer 111 has a first surface 111a and a second surface 111b opposite to each other, and the first dielectric layer 111 covers the first patterned circuit layer 112b and the first bump 112 a. Then, at least two second patterned circuit layers 115 (schematically shown as 4 layers in fig. 1G), at least one second dielectric layer 116 (schematically shown as 3 layers in fig. 1G), and at least one first conductive via 117 (schematically shown as 11 in fig. 1G) are optionally formed on the first dielectric layer 111. Specifically, the second patterned circuit layer 115 and the second dielectric layer 116 are sequentially stacked on the second surface 111b of the first dielectric layer 111. The first conductive via 117 penetrates the second dielectric layer 116. The second patterned circuit layer 115 is electrically connected to another second patterned circuit layer 115 through the first conductive via 117.

Then, referring to fig. 1H, the core layer 210, the first patterned copper layer 220 and the nickel layer 230 are removed to expose the first bump 112a and the first patterned circuit layer 112 b. In the present embodiment, the steps of removing the core layer 210, the first patterned copper layer 220 and the nickel layer 230 are, for example: the plate-detaching process is performed to separate the copper foil layer 216a from the release layer 214a, and then the copper foil layer 216a, the first patterned copper layer 220 and the nickel layer 230 are removed in sequence by etching. It should be noted that although the present embodiment discloses the step of removing the core layer 210, the first patterned copper layer 220 and the nickel layer 230, the invention is not limited thereto.

Then, referring to fig. 1I and fig. 1J, a portion of the first patterned circuit layer 112b is removed to form a recess 113 and expose a portion of the first dielectric layer 111. In the present embodiment, the step of removing a portion of the first patterned circuit layer 112b to form the groove 113 includes, for example: first, the area of the first dielectric layer 111 and the first patterned circuit layer 112b except the predetermined region 113 covered by the third patterned photoresist layer R3, such as a dry film, is etched to remove the portion of the first patterned circuit layer 112b not covered by the third patterned photoresist layer R3, so as to form the recess 113 and expose the portion of the first dielectric layer 111. At this time, the first dielectric layer 111 also has a third surface 111 c. The third surface 111c is located on the portion of the first dielectric layer 111 exposed by the recess 113, and the third surface 111c is aligned with the lower surface 112b1 of the first patterned circuit layer 112 b. It should be noted that although the present embodiment discloses the step of removing a portion of the first patterned circuit layer 112b to form the recess 113, the invention is not limited thereto. At this point, the circuit structure 110 is completed.

Next, referring to fig. 1K, the embedded substrate 120 is disposed in the groove 113 of the circuit structure 110. The buried substrate 120 includes a plurality of second bumps 121 (schematically shown as 6 in fig. 1K), at least one dielectric layer 122 (schematically shown as 3 layers in fig. 1K), at least one patterned conductive layer 123 (schematically shown as 2 layers in fig. 1K), and at least one conductive via 124 (schematically shown as 2 in fig. 1K). In the present embodiment, the buried substrate 120 is adhered and fixed on the third surface 111c of the first dielectric layer 111 by using the glue layer 125, and the second bump 121 of the buried substrate 120 is flush with the first bump 112a of the circuit structure 110. Here, the material of the embedded substrate may be an organic material, such as photosensitive polyimide (polyimide), other photosensitive imageable dielectric material (PID), or other suitable organic materials, but not limited thereto. In some other embodiments, the material of the embedded substrate may also be an inorganic material, such as, but not limited to, glass, silicon dioxide, other ceramic materials, silicon chip (silicon chip), or other semiconductors.

Then, referring to fig. 1L and fig. 1M, a patterned solder mask layer 119a is formed on the bottom surface 116a of the circuit structure 110 relatively far from the first patterned circuit layer 112b and a patterned solder mask layer 118a is formed on the first surface 111a of the first dielectric layer 111. Then, the solder mask layer 118 is disposed on the first surface 111a of the first dielectric layer 111, and the solder mask layer 119 is disposed on the bottom surface 116a of the circuit structure 110 relatively far away from the first patterned circuit layer 112 b. That is, the solder mask layer 118 covers the first dielectric layer 111, the first patterned circuit layer 112b and the embedded substrate 120, and the solder mask layer 119 covers the second patterned circuit layer 115 and the second dielectric layer 116 which are farthest from the first patterned circuit layer 112 b. Then, the solder mask layer 118 is thinned to form a patterned solder mask layer 118a and expose the first bumps 112a of the circuit structure 110 and the second bumps 121 of the embedded substrate 120. The solder mask 119 is patterned to form a patterned solder mask 119a and expose a portion of the second patterned circuit layer 115 farthest from the first patterned circuit layer 112 b. Here, the solder mask layer 118 and the solder mask layer 119 are formed by, for example, an inkjet method, but not limited thereto. At this time, the circuit carrier 100 with the embedded substrate is completed.

In view of the above, in the present embodiment, the circuit carrier 100 with an embedded substrate includes the circuit structure 110 and the embedded substrate 120. The circuit structure 110 includes a first dielectric layer 111, a first patterned circuit layer 112b, a recess 113, and a plurality of first bumps 112 a. The first dielectric layer 111 has a first surface 111a and a second surface 111b opposite to each other. The first patterned circuit layer 112b is buried in the first surface 111 a. The first bump 112a is disposed on the first surface 111 a. The first bump 112a is electrically connected to the first patterned circuit layer 112 b. The recess 113 exposes a portion of the first dielectric layer 111. The embedded substrate 120 is disposed in the groove 113, and the embedded substrate 120 includes a second bump 121.

It should be noted that the following embodiments follow the reference numerals and parts of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

Fig. 2 is a schematic cross-sectional view illustrating a chip package structure according to an embodiment of the invention.

In this embodiment, the chip package structure 10 includes a circuit carrier 100 having a buried substrate, a first chip 310 and a second chip 320. The first chip 310 is disposed on the circuit structure 110 of the circuit carrier 100 having the embedded substrate, and the second chip 320 is disposed on the circuit structure 110 of the circuit carrier 100 having the embedded substrate. The first chip 310 is electrically connected to the circuit structure 110 through the first bump 112a, and the first chip 310 is electrically connected to the embedded substrate 120 through the second bump 121. The second chip 320 is electrically connected to the circuit structure 110 through the first bump 112a, and the second chip 320 is electrically connected to the embedded substrate 120 through the second bump 121.

In detail, the first chip 310 includes a plurality of first solder balls 312 (schematically shown as 8 in fig. 2) and the second chip 320 includes a plurality of second solder balls 322 (schematically shown as 8 in fig. 2). The first chip 310 may be electrically connected to the first patterned circuit layer 112b and the embedded substrate 120 through first solder balls 312, and the second chip 320 may be electrically connected to the first patterned circuit layer 112b and the embedded substrate 120 through second solder balls 322.

In summary, in the circuit carrier with an embedded substrate, the manufacturing method thereof and the chip package structure of the invention, since the circuit structure includes the groove, the embedded substrate can be disposed in the groove, and the first chip and the second chip can be electrically connected to the circuit structure through the first bump respectively, and the first chip and the second chip can be electrically connected to the embedded substrate through the second bump respectively. By the design, the circuit carrier plate with the embedded substrate can integrate various different chips and has thinner thickness, and the chip packaging structure has thinner packaging thickness and smaller packaging volume.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.