阅读说明：本技术 半导体装置封装及其制造方法 (Semiconductor device packages and its manufacturing method ) 是由 涂顺财 罗培仁 林彦熙 郭千琦 于 2018-07-20 设计创作，主要内容包括：一种半导体装置封装包含衬底、第一线圈、介电层和第二线圈。所述第一线圈安置在所述衬底上。所述第一线圈包含第一导电段和第二导电段。所述介电层覆盖所述第一线圈的所述第一导电段和所述第一线圈的所述第二导电段,且界定所述第一线圈的所述第一导电段与所述第一线圈的所述第二导电段之间的第一凹部。所述第二线圈安置在所述介电层上。所述第二线圈具有安置在所述第一凹部内的第一导电段。(A kind of semiconductor device packages include substrate, first coil, dielectric layer and the second coil.The first coil placement is over the substrate.The first coil includes the first conductive segment and the second conductive segment.The dielectric layer covers first conductive segment of the first coil and second conductive segment of the first coil, and defines the first recess portion between first conductive segment of the first coil and second conductive segment of the first coil.The second coil placement is on the dielectric layer.Second coil has the first conductive segment being placed in first recess portion.)

1. a kind of semiconductor device packages comprising:

Substrate；

First coil, over the substrate, the first coil includes the first conductive segment and the second conductive segment for placement；

Dielectric layer covers first conductive segment of the first coil and second conductive segment of the first coil, And it defines first recessed between first conductive segment of the first coil and second conductive segment of the first coil Portion；And

Second coil, on the dielectric layer, second coil includes first be placed in first recess portion for placement Conductive segment.

2. semiconductor device packages according to claim 1, wherein

The first coil further include placement over the substrate with second conductive segment of first conductive coil Third conductive segment spaced apart；

The dielectric layer covers the third conductive segment of the first coil, and defines described the second of the first coil and lead The second recess portion between electric section and the third conductive segment of the first coil；And

Second coil further includes the second conductive segment being placed in second recess portion.

It further comprise across described the of the first coil 3. semiconductor device packages according to claim 2 Two conductive segments dispose and first conductive segment of second coil are electrically connected to described the second of second coil and lead First connection structure of electric section.

4. semiconductor device packages according to claim 3, wherein the thickness of first connection structure is less than described the The thickness of first conductive segment of the thickness or second coil of first conductive segment of one coil.

5. semiconductor device packages according to claim 1, wherein first conductive segment of the first coil and institute First conductive segment for stating the second coil is overlapped on the direction of top surface for being parallel to the substrate.

6. semiconductor device packages according to claim 1, wherein

First conductive segment of the first coil has the top surface back to the top surface of the substrate；

First conductive segment of second coil has the bottom surface for the top surface for facing the substrate；And

Between the top surface of first conductive segment and the top surface of the substrate of the first coil Distance be greater than second coil first conductive segment the bottom surface and the substrate the top surface it Between distance.

7. semiconductor device packages according to claim 1, further comprise the first coil is connected to it is described Second connection structure of the second coil.

8. semiconductor device packages according to claim 1, wherein the first coil separated with second coil and It is magnetically coupled to second coil.

9. semiconductor device packages according to claim 1, wherein electric current and second line in the first coil Electric current in circle flows in a same direction.

10. a kind of semiconductor device packages comprising:

Substrate, with top surface；

First coil is placed on the top surface of the substrate, and the first coil includes the first conductive segment；

Dielectric layer covers first conductive segment and second conductive segment；And

Second coil, on the dielectric layer, second coil includes the first conductive segment for placement,

Wherein first conductive segment of first conductive segment Yu second coil of the first coil is generally flat Row is overlapped on the direction of the top surface of the substrate.

11. semiconductor device packages according to claim 10, wherein

Second coil further includes the second conductive segment of first conductive segment adjacent to second coil；And

First conductive segment of the first coil is placed in first conductive segment and described second of second coil Between second conductive segment of coil.

12. semiconductor device packages according to claim 11 further comprise across the described of the first coil First conductive segment disposes and first conductive segment of second coil is electrically connected to described the second of second coil First connection structure of conductive segment.

13. semiconductor device packages according to claim 12, wherein the thickness of first connection structure is less than described The thickness of first conductive segment of the thickness or second coil of first conductive segment of first coil.

14. semiconductor device packages according to claim 11, wherein

First conductive segment of the first coil has the top surface back to the top surface of the substrate；

First conductive segment of second coil has the bottom surface for the top surface for facing the substrate；And

Between the top surface of first conductive segment and the top surface of the substrate of the first coil Distance be greater than second coil first conductive segment the bottom surface and the substrate the top surface it Between distance.

15. semiconductor device packages according to claim 11 further comprise that the first coil is connected to institute State the second connection structure of the second coil.

16. semiconductor device packages according to claim 11, wherein the first coil is separated with second coil And it is magnetically coupled to second coil.

17. semiconductor device packages according to claim 11, wherein the electric current and described second in the first coil Electric current in coil flows in a same direction.

18. a kind of semiconductor device packages comprising:

Substrate, with top surface；

First coil is placed on the top surface of the substrate, and the first coil includes multiple conductive segments；

Dielectric layer covers the first coil, and the recess portion between the neighbouring conductive segment of two for defining the first coil；With And

Second coil, on the dielectric layer, second coil includes multiple conductive segments for placement,

Wherein one in the multiple conductive segment of second coil disposes within the recess.

19. semiconductor device packages according to claim 18 further comprise two of connection second coil Pacify adjacent to conductive segment and across the conductive segment of the first coil between described two neighbouring conductive segments of second coil The connection structure set.

20. semiconductor device packages according to claim 19, wherein the thickness of the connection structure is less than described first The thickness of any of the conductive segment of the thickness of any of the conductive segment of coil or second coil.

Technical field

This disclosure relates to a kind of semiconductor device packages and its manufacturing method, and include figure more specifically to one kind The semiconductor device packages and its manufacturing method of case.

Background technique

With the development of system encapsulation (SIP), passive electric components (for example, capacitor, inductor or transformer) can be through It is integrated in encapsulation (that is, integrated-type passive device, IPD).For the inductance for increasing the inductor being integrated in encapsulation, electricity should be increased The number of turns of sensor.However, this will also increase the size of packaging system.Another method is to stack two coils.However, this will increase The thickness of packaging system.

Summary of the invention

According to some embodiments of the present disclosure, a kind of semiconductor device packages include substrate, first coil, dielectric layer and the Two coil.First coil disposes on substrate.First coil includes the first conductive segment and the second conductive segment.Dielectric layer covering first First conductive segment of coil and the second conductive segment of first coil, and define the first conductive segment and first coil of first coil The first recess portion between second conductive segment.Second coil disposes on the dielectric layer.Second coil, which has, to be placed in the first recess portion The first conductive segment.

According to some embodiments of the present disclosure, a kind of semiconductor device packages include substrate, first coil, dielectric layer and the Two coil.Substrate has top surface.First coil disposes on the top surface of the substrate.First coil has the first conduction Section.Dielectric layer covers the first conductive segment and the second conductive segment.Second coil disposes on the dielectric layer.Second coil has first to lead Electric section.First conductive segment of first coil and the first conductive segment of the second coil are in the top surface for being substantially parallel to substrate It is overlapped on direction.

According to some embodiments of the present disclosure, a kind of semiconductor device packages include substrate, first coil, dielectric layer and the Two coil.Substrate has top surface.First coil disposes on the top surface of the substrate.First coil has multiple conductions Section.Dielectric layer covers first coil, and the recess portion between the neighbouring conductive segment of two for defining first coil.Second coil is placed in On dielectric layer.Second coil has multiple conductive segments.One in multiple conductive segments of second coil is placed in recess portion.

Detailed description of the invention

Figure 1A illustrates the viewgraph of cross-section of the semiconductor device packages according to some embodiments of the present disclosure.

Figure 1B illustrates the top view of the semiconductor device packages in Figure 1A according to some embodiments of the present disclosure.

Fig. 2 illustrates the viewgraph of cross-section of the semiconductor device packages according to some embodiments of the present disclosure.

Fig. 3 A illustrates the perspective view of the inductor according to some embodiments of the present disclosure.

Fig. 3 B illustrates the viewgraph of cross-section of the inductor in Fig. 3 A according to some embodiments of the present disclosure.

Fig. 4 A, Fig. 4 B, Fig. 4 C, Fig. 4 D, Fig. 4 E and Fig. 4 F illustrate the semiconductors manufacture according to some embodiments of the present disclosure Method.

Fig. 5 A and Fig. 5 B illustrate the semiconductor making method according to some embodiments of the present disclosure.

Same or like component is indicated using common reference numerals through schema and detailed description.According to below in conjunction with attached Scheme the detailed description carried out, the disclosure will will be more fully apparent.

Specific embodiment

Figure 1A illustrates the viewgraph of cross-section of the semiconductor device packages 1 according to some embodiments of the present disclosure.Semiconductor dress Setting encapsulation 1 includes: substrate 10, patterned conductive layer 11,12, dielectric layer 13 and packaging body 14.

Substrate 10 can soak for (for example) printed circuit board, such as paper base copper foil laminates, composite copper foil laminates or polymer The glass fibre class copper foil laminates of stain.In some embodiments, substrate 10 can be (for example) glass substrate.Substrate 10 may include Interconnection structure (or electrical connection), such as redistribution layer (RDL) or earth element.Substrate 10 may include surface 101 and opposite with surface 101 Surface 102.

Patterned conductive layer 11 is placed on the surface 101 of substrate 10.Patterned conductive layer 11 is that such as metal or metal close The conductive materials such as gold, or include the conductive materials such as such as metal or metal alloy.Example includes gold (Au), silver (Ag), aluminium (Al), copper (Cu) or its alloy.As shown in Figure 1A, patterned conductive layer 11 includes the viewgraph of cross-section from semiconductor device packages 1 Multiple section 11a, 11b, 11c.Section 11a, 11b, 11c are separated from each other.For example, the adjacent section (example of section 11a Such as, section 11b) it is spaced apart, and the adjacent section of section 11b (for example, section 11a and section 11c) is spaced apart.Citing comes Say, recess portion (or gap) be defined in two adjacent segments (for example, section 11a and section 11b or section 11b and section 11c) it Between.

Dielectric layer 13 (or passivation layer) is placed on the surface 101 and patterned conductive layer 11 of substrate 10.For example, it is situated between Electric layer 13 is conformally placed on patterned conductive layer 11.In some embodiments, the thickness of dielectric layer 13 is generally uniform.It is situated between At least part of 13 overlay pattern conductive layer 11 of electric layer.For example, the area of 13 overlay pattern conductive layer 11 of dielectric layer The top surface and side wall (side surface) of section 11a, 11c.For example, the section of 13 overlay pattern conductive layer 11 of dielectric layer The top surface of 11b and a part of side wall, and remainder of the exposure for the top surface of the section 11b of electrical connection.In In some embodiments, dielectric layer 13 include polymer, silica, nitrogen oxides, gallium oxide, aluminium oxide, scandium oxide, zirconium oxide, Lanthana or hafnium oxide.

Patterned conductive layer 12 is placed on dielectric layer 13.Patterned conductive layer 12 is such as metal or metal alloy conduction Material, or include the conductive materials such as such as metal or metal alloy.In some embodiments, patterned conductive layer 12 and conductive layer 11 It may include identical material.Alternatively, patterned conductive layer 12 and conductive layer 11 include different materials.As shown in Figure 1A, scheme Case conductive layer 12 includes multiple section 12a, 12b, 12c of the viewgraph of cross-section from semiconductor device packages 1.Section 11a, 11b, 11c are placed in the recess portion defined by patterned conductive layer 11 or gap.For example, section 12a is placed in by pattern In the recess portion that the section 11a and its adjacent segments for changing conductive layer 11 are defined, section 12b is placed in by the area of patterned conductive layer 11 In the recess portion that section 11a and section 11b is defined, and section 12c is placed in the section 11b and section 11c by patterned conductive layer 11 In the recess portion defined.For example, a part of patterned conductive layer 12 (including section 12a, 12b and 12c) and patterning are led A part of electric layer 11 (including section 11a, 11b and 11c) weight on the direction on the surface 101 for being substantially parallel to substrate 10 It is folded.For example, (the also referred to as top table of surface 111 of each of section 11a, 11b, 11c of patterned conductive layer 11 Face) it is greater than each of section 12a, 12b, 12c of patterned conductive layer 12 with the distance between the surface 101 of substrate 10 The distance between the surface 101 on surface 122 (also referred to as bottom surface) and substrate 10.

Section 12a, 12b, 12c are physically separated from each other.For example, the adjacent section of section 12a is (for example, area Section 1bb) it is spaced apart, and the adjacent section of section 12b (for example, section 12a and section 12c) is spaced apart.In some embodiments In, section 12b and section 12c are electrically connected by connection structure 15.Patterned conductive layer 12 is led by dielectric layer 13 with patterning Electric layer 11 is spaced apart.For example, dielectric layer 13 is placed between patterned conductive layer 12 and patterned conductive layer 11.Some In embodiment, patterned conductive layer 12 and patterned conductive layer 11 are electrically connected to form or are defined such as Figure 1B by connection structure 15 Shown in inductor (or coil), described Figure 1B illustrates according to the semiconductor device packages 1 of some embodiments of the present disclosure Top view.For example, the section 11b of connection structure 15 across patterned conductive layer 11 is disposed with connecting pattern conductive layer 12 Section 12b and section 12c.For example, as shown in fig. 1b, an end of patterned conductive layer 11 is electrically connected to pattern Change an end of conductive layer 12 to define inductor.In some embodiments, the thickness D11 of connection structure 15 is less than patterning The thickness of section 12a, 12b or 12c of the thickness D12 or patterned conductive layer 12 of section 11a, 11b or 11c of conductive layer 11 D13。

Patterned conductive layer 11 and patterned conductive layer 12, which jointly define, can be magnetically coupled to magnetic field in pattern conductive The inductor of inducing current in layer 11 and 12.For example, the electric current in patterned conductive layer 11 and patterned conductive layer 12 exists It is flowed on identical direction (for example, in the clockwise direction or in the counterclockwise direction).Because of connecting pattern conductive layer 11 With patterned conductive layer 12, so the total number of turns of the inductor defined by patterned conductive layer 11 and patterned conductive layer 12 increases Add, this will transfer the inductance of increase inductor.

In some embodiments, the inductance of the inductor with single coil can be increased by increasing the number of turns of single coil Greatly.However, this will also increase the size (for example, area) of inductor.In some embodiments, it directly can stack and connect two A coil is to increase the inductance of inductor.For example, a coil is being parallel to peace without any lap It sets and is placed on another coil on the direction of the top surface of the substrate of coil, this will increase the thickness of inductor.According to Figure 1A With the embodiment in 1B, upper coil (for example, patterned conductive layer 12) is placed in lower coil (for example, patterned conductive layer 11) top, while the section (for example, section 12a, 12b, 12c) of upper coil be joined to by lower coil section (for example, Section 11a, 11b, 11c) recess portion that defines or gap, this allows inductor (comprising upper coil and lower coil) not increasing Increase inductance in the case where the area or thickness of semiconductor device packages 1.In some embodiments, with the stacking of non-overlapping part Coil is compared, and the thickness of inductor as shown in Figure 1A can be reduced by about 30% to 35%.

Packaging body 14 is placed on substrate 10 with overlay pattern conductive layer 11,12, dielectric layer 13 and connection structure 15.In In some embodiments, packaging body 14 includes the epoxy resin comprising filler, mold compound (for example, epoxy molding compounds Or other mold compounds), polyimides, phenolic compounds or material, the material comprising organosilicon dispersed therein or its group It closes.

Fig. 2 illustrates the viewgraph of cross-section of the semiconductor device packages 2 according to some embodiments of the present disclosure.Semiconductor device Encapsulation 2 is similar to the semiconductor device packages 1 in Figure 1A, makes an exception as in semiconductor device packages 2, conductive patterned layers 12 with Conductive pattern layer 11 separates.For example, conductive patterned layers 12 are not electrically connected to conductive pattern layer 11.For example, it saves Connection structure 15 in sketch map 1A.In some embodiments, conductive patterned layers 12 are magnetically coupled to conductive pattern layer 11 to be formed Or define transformer.For example, conductive patterned layers 11 are the primary side winding of transformer, and conductive patterned layers 12 are to become The primary side winding of depressor, and vice versa.

Fig. 3 A illustrates the perspective view of the inductor 3 according to some embodiments of the present disclosure.Inductor 3 includes to be placed in stacking Coil 31a, 31b, 32a and 32b in structure.Illustrate inductor 3 viewgraph of cross-section Fig. 3 B as shown in, coil 31a and Coil 32a is arranged in a manner of the arrangement of the patterned conductive layer 11 and patterned conductive layer 12 that are similar in Figure 1A.Citing For, a part of coil 31a and a part overlapping of coil 31b.For example, the section of coil 31b is placed in by coil In recess portion that the section of 31a defines or gap.Structure 32 comprising coil 32a and 32b, which is similar to, includes coil 31a and 31b Structure 31.With comprising two stacked coils as shown in Figure 1A and 1B (that is, patterned conductive layer 11 and patterned conductive layer 12) inductor is compared, and the inductor 3 comprising four stacked coils 31a, 31b, 32a and 32b has more multiturn coil, this will Increase the inductance of inductor 3.

Fig. 4 A, 4B, 4C, 4D, 4E and 4F illustrate the semiconductor making method according to some embodiments of the present disclosure.Some In embodiment, implement the operation in Fig. 4 A to manufacture the semiconductor device packages 1 in Figure 1A and 1B.Alternatively, implementable figure Operation in 4A is to manufacture other semiconductor device packages or inductor or transformer (for example, the semiconductor device packages in Fig. 2 With the inductor 3 in Fig. 3 A and 3B).

With reference to Fig. 4 A, substrate 10 is provided.Patterned conductive layer 11 is formed on substrate 10.Patterned conductive layer 11 is such as gold The conductive materials such as category or metal alloy, or include the conductive materials such as such as metal or metal alloy.Such as illustrate patterned conductive layer 11 Top view Fig. 5 A shown in, patterned conductive layer 11 defines spiral inductor.As shown in Figure 4 A, patterned conductive layer 11 Include the multiple sections being separated from each other.Multiple recess portion (or gap) 11h are defined between two adjacent segments.

Dielectric layer 13 (or passivation layer) is formed on substrate 10 and patterned conductive layer 11.For example, dielectric layer 13 is total It is formed in shape on patterned conductive layer 11.In some embodiments, the thickness of dielectric layer 13 is generally uniform.In some implementations Example in, dielectric layer 13 include polymer, silica, nitrogen oxides, gallium oxide, aluminium oxide, scandium oxide, zirconium oxide, lanthana or Hafnium oxide.

With reference to Fig. 4 B, photoresist (or mask) 49 is placed on dielectric layer 13.Opening 49h1 is formed to removal 49 He of photoresist A part of dielectric layer 13 is to expose substrate 10.Opening 49h2 is formed to a part of removal photoresist 49 and dielectric layer 13 with sudden and violent Reveal a part of the section 11b of patterned conductive layer 11.In some embodiments, opening 49h1,49h2 can pass through drilling, laser Drilling, etching or other suitable techniques are formed.In some embodiments, opening 49h1,49h2 can be operated by single removal It is formed.In some embodiments, opening 49h1,49h2 can be formed by two removal operations.For example, implement the first removal Operation implements the second removal operation then to remove photoresist 49 to remove dielectric layer 13.

With reference to Fig. 4 C, photoresist 49 is removed, and seed layer 49s is formed in dielectric layer 13 and the substrate from the exposure of dielectric layer 13 In 10 a part and section 11b.In some embodiments, seed layer 49s is for example, by sputter or other suitable technique shapes At.

With reference to Fig. 4 D, photoresist 48 (or mask) is placed on seed layer 49s, and remove photoresist 48 a part with exposure by One of recess portion 11h that section 11a, 11b, 11c of patterned conductive layer 11 are defined, the seed layer 49s being placed on section 11b Point and substrate 10.In some embodiments, the part of photoresist 48 can pass through drilling, laser drill, etching or other suitable Technique is formed.In some embodiments, the part of photoresist 48 may depend on design requirement and operate or multiple go by single removal Except operation removes.

With reference to Fig. 4 E, patterned conductive layer 12 and connection structure 15 are formed for example, by plating or other suitable techniques. For example, illustrate patterned conductive layer 12 top view Fig. 5 B as shown in, patterned conductive layer 12 define be placed in by The spiral inductor in recess portion 11h that the section of patterned conductive layer 11 defines.For example, as shown in figure 4e, pattern Conductive layer 12 includes multiple section 12a, 12b, the 12c being placed in the recess portion defined by the section of patterned conductive layer 11.Figure Case conductive layer 12 is such as metal or metal alloy conductive material, or includes the conductive materials such as such as metal or metal alloy.

With reference to Fig. 4 F, a part of the seed layer 49s not contacted with patterned conductive layer 12 for example, by etching (for example, Wet etching) or other suitable technique removals.Then, packaging body 14 is formed to overlay pattern conductive layer 11,12, dielectric Layer 13 and connection structure 15 form semiconductor device packages 4.In some embodiments, packaging body 14 can be for example, by shifting mould It makes or compression molded equal molding techniques is formed.Semiconductor device packages 4 are similar to the semiconductor device packages 1 in Figure 1A, exception The seed layer 49s between patterned conductive layer 12 and dielectric layer 13 is further included for semiconductor device packages 4.

As used herein, term " generally ", " substantially ", " approximation " and " about " it is used to indicate and explains small change Change.For example, when in conjunction with numerical value in use, term can refer to ± 10% variation range less than or equal to the numerical value, such as Less than or equal to ± 5%, be less than or equal to ± 4%, be less than or equal to ± 3%, be less than or equal to ± 2%, being less than or equal to ± 1%, it is less than or equal to ± 0.5%, is less than or equal to ± 0.1%, or is less than or equal to ± 0.05%.As another example, film Or the thickness " generally uniform " of layer can refer to the standard deviation for being less than or equal to ± 10% of the average thickness of film or layer, such as small In or be equal to ± 5%, be less than or equal to ± 4%, be less than or equal to ± 3%, be less than or equal to ± 2%, be less than or equal to ± 1%, it is less than or equal to ± 0.5%, is less than or equal to ± 0.1%, or is less than or equal to ± 0.05%.Term " substantially coplanar " It can refer to two surfaces to be in a few micrometers along same plane, such as in 40 μm, in 30 μm, in 20 μm, in 10 μm or in 1 μm In along same plane.If two angles between surface or component be such as 90 ° ± 10 °, for example, ± 5 °, ± 4 °, ± 3 °, ± 2 °, ± 1 °, ± 0.5 °, ± 0.1 ° or ± 0.05 °, then two surfaces or component visual are " generallyperpendicular ".Work as combination Event or situation are in use, term " generally ", " substantially ", " approximation " and " about " can refer to the example that event or situation accurately occur Son and the example of the very approximate appearance of event or situation.

In the description of some embodiments, the component for being provided in another component "upper" can cover previous component directly latter The case where on component (for example, with latter assemblies physical contact) and one or more intermediate modules be located at previous component with it is latter The case where between component.

In addition, sometimes herein with range format presentation amount, ratio and other numerical value.It should be understood that this kind of range format Is used in order to convenient and succinct, and should neatly understand, not only include be expressly specified as the numerical value of range limit, but also Comprising all individual numbers or the subrange being covered by the range, as explicitly specified each numerical value and subrange one As.

Although describing and illustrating the disclosure referring to the specific embodiment of the disclosure, these descriptions and instructions are not intended to limit The disclosure.Those skilled in the art can be clearly understood that, not depart from the disclosure as defined by the appended claims True spirit and range in the case where, various changes can be carried out, and equivalence element can be replaced in embodiment.Schema may be not It must be drawn to scale.Due to the parameter etc. in manufacturing process, may be deposited between the art recurring and physical device in the disclosure It is distinguishing.The other embodiments of the not disclosure of certain illustrated may be present.This specification and schema should be considered as it is illustrative and It is unrestricted.It can modify, so that particular condition, material, material composition, method or technique are suitable for the mesh of the disclosure Mark, spirit and scope.All such modifications are intended within the scope of the appended claims.Although being held referring to by certain order Capable specific operation describes method disclosed herein, it should be appreciated that can the teaching for not departing from the disclosure the case where the following group These operations are closed, segment or resequenced to form equivalent method.Therefore, unless special instructions herein, time otherwise operated Sequence and grouping are not the limitation of the disclosure.