阅读说明：本技术 一种基于阵列式孔道的二级激发自毁芯片及其制备方法 (Array-type-pore-channel-based secondary excitation self-destruction chip and preparation method thereof ) 是由 任丁 邵梦凡 刘波 昂然 林黎蔚 于 2021-02-08 设计创作，主要内容包括：本发明公开了一种基于阵列式孔道的二级激发自毁芯片及其制备方法,该二级激发自毁芯片包括基底层和自毁结构；基底层为目标芯片；自毁结构设置于目标芯片的背面,包括加热电路、若干孔道以及含能材料层,道阵列式排布于目标芯片上的拟损毁区域,含能材料层覆盖加热电路的加热区以及孔道阵列区域,加热电路串联于外部控制单元和供电单元构成的电路回路中。该自毁芯片通过常规芯片制备工艺即可制备。该自毁芯片采用弱电流激发-化学燃爆的二级激发结构,在半导体基体上设置阵列式孔道、深孔等三维结构以降低基体强度,从而实现目标芯片的粉碎性损伤,通过两种技术手段实现了低功耗工况条件下对目标芯片的彻底销毁,从而确保了芯片的信息安全。(The invention discloses a secondary excitation self-destruction chip based on an array type pore channel and a preparation method thereof, wherein the secondary excitation self-destruction chip comprises a substrate layer and a self-destruction structure; the substrate layer is a target chip; the self-destruction structure is arranged on the back of the target chip and comprises a heating circuit, a plurality of pore channels and an energetic material layer, the pore channels are arranged in an array mode in a to-be-destroyed area on the target chip, the energetic material layer covers a heating area of the heating circuit and the pore channel array area, and the heating circuit is connected in series in a circuit loop formed by an external control unit and a power supply unit. The self-destruction chip can be prepared by a conventional chip preparation process. The self-destruction chip adopts a secondary excitation structure of weak current excitation-chemical explosion, and three-dimensional structures such as array type pore canals and deep holes are arranged on a semiconductor substrate to reduce the strength of the substrate, so that the target chip is crushed and damaged.)

1. A two-stage excitation self-destruction chip based on array type pore channels is characterized in that: comprises a substrate layer and a self-destruction structure;

the base layer is a target chip (5);

the self-destruction structure is arranged on the back of a target chip (5) and comprises a heating circuit, a plurality of pore channels (4) and an energetic material layer (6), the pore channels are arranged in a to-be-destroyed area on the target chip (5) in an array mode, the energetic material layer (6) covers a heating area of the heating circuit and at least part of the pore channel array area, and the heating circuit is connected in series in a circuit loop formed by an external control unit and a power supply unit.

2. The array-type pore passage-based secondary excitation self-destruction chip as claimed in claim 1, wherein: the external control unit comprises a photosensitive switch (7) or/and a force-sensitive switch (8), and two ends of the photosensitive switch (7) or/and the force-sensitive switch (8) are respectively connected to the heating circuit and the power supply unit.

3. The array-type pore channel-based secondary excitation self-destruction chip as claimed in claim 2, wherein: the heating circuit comprises an electrode pad (1), two metal wires (2) and a heating wire (3), the electrode pad (1) comprises an anode pad and a cathode pad, the anode pad and the cathode pad are respectively connected with one metal wire (2), the end parts of the two ends of the heating wire (3) are respectively connected with the two metal wires (2), the anode pad and the cathode pad are respectively connected with an external control unit and a power supply unit, and the heating wire (3) is a heating area of the heating circuit.

4. The array-type pore channel-based secondary excitation self-destruction chip as claimed in claim 3, wherein: the width of the heating wire (3) is 2-50 microns, the wire length is 500-50000 microns, the length-width ratio is 200-5000, and the wire thickness is 200-1000 nanometers.

5. The array-type pore channel-based secondary excitation self-destruction chip according to any one of claims 1 to 4, wherein: the pore space of the pore canal array is 20-200 microns, the pore diameter of the pore canal (4) is 10-100 microns, and the depth of the pore canal (4) is 20-200 microns; the cross section of the pore canal (4) is circular, rectangular or regular polygon.

6. The method for preparing the array-type pore channel-based secondary excitation self-destruction chip as claimed in any one of claims 1 to 5, wherein the method comprises the following steps: the method comprises the following steps:

s1, preparing an insulating layer on the back of the substrate, and depositing a metal conducting layer on the surface of the insulating layer;

s2, etching the metal conductive layer into a heating circuit by adopting a photoetching process;

s3, etching a pore array by using a photoetching process beside the heating circuit on the substrate according to the region to be damaged, wherein the pore array covers the region to be damaged of the target chip;

s4, coating an energetic material layer on the back of the substrate by adopting a coating process, wherein the energetic material layer covers a heating area of the heating circuit and at least part of the pore array area;

s5, the heating circuit may be connected to an external control unit and a power supply unit.

7. The method for preparing the array-type pore channel-based secondary excitation self-destruction chip according to claim 6, wherein the array-type pore channel-based secondary excitation self-destruction chip comprises the following steps: in step S5, a light-sensitive switch and a force-sensitive switch connected in parallel are connected between the power supply unit and the heating circuit.

8. The method for preparing the array-type pore channel-based secondary excitation self-destruction chip according to claim 6, wherein the array-type pore channel-based secondary excitation self-destruction chip comprises the following steps: the step S1 specifically includes the following steps:

s11, cleaning preparation: cleaning and drying a substrate containing a silicon substrate for later use;

s12, preparing an oxide film: after the treatment of step S11, the substrate is placed in a thermal oxidation furnace, the cavity of the oxidation furnace is sealed and vacuumized to be lower than 10 DEG^-1Pa, introducing oxygen, heating the heating furnace body to 1050-1150 ℃ at the temperature rise rate of 15-25 ℃/min, preserving the temperature for 10-20 minutes and then performing heat preservationCooling to below 400 ℃ at a cooling rate of 15-25 ℃/min, and naturally cooling to room temperature to form a silicon dioxide oxide film, namely an insulating layer;

s13, coating: after the treatment of the step S12, the substrate is placed on a sample table of a film coating machine and is vacuumized to 10 DEG^-3Pa below, at 15-25cm³Argon is filled to 0.2-0.8Pa at the flow rate of/min, sputtering coating is carried out on the metal target material to form a metal film, namely a metal conductive layer, the coating time is 5-20min, and then the metal film is naturally cooled to the room temperature.

9. The method for preparing the array-type pore channel-based secondary excitation self-destruction chip according to claim 8, wherein the method comprises the following steps: the step S2 specifically includes the following steps:

s21, gluing, spinning and soft drying: placing the coated substrate on a glue spreader, dripping glue, then performing glue throwing, heating to 100-120 ℃ in vacuum, and performing soft drying treatment for 30-60 seconds;

s22, exposure and postbaking: after the processing of the step S21, placing the substrate on a sample platform of an exposure machine, copying a heating circuit diagram on the photoresist, and then placing the substrate in an environment with the temperature of 110-;

s23, developing and hard baking: after the processing of the step S22, spraying the developing solution on the surface of the substrate for developing, then placing the substrate in an environment with the temperature of 110-130 ℃ for heat preservation for 1-3min for hard baking treatment, and exposing the heating circuit pattern;

s24, etching: after the treatment of the step S23, putting the substrate in an etching machine, introducing chlorine as working gas for ionization to carry out dry etching on the metal film, and removing the redundant metal film;

s25, removing the photoresist: after the treatment of step S24, the excess photoresist is removed by acetone and isopropanol in sequence, and then the substrate is cleaned by deionized water and dried.

10. The method for preparing the array-type pore channel-based secondary excitation self-destruction chip according to claim 9, wherein the method comprises the following steps: the step S3 specifically includes the following steps:

s31, gluing, spinning and soft drying: after the treatment of the step S25, placing the substrate on a glue spreader, dripping glue, then performing glue throwing, heating to the temperature of 100-;

s32, exposure and postbaking: after the treatment of the step S31, the substrate is placed on a sample platform of an exposure machine, the pore pattern is copied on the photoresist, and then the substrate is placed in an environment with the temperature of 110-;

s33, developing and hard baking: after the treatment of the step S32, spraying the developing solution on the surface of the substrate for development, and then placing the substrate in an environment with the temperature of 110-130 ℃ for heat preservation for 1-3min for hard baking treatment to expose the pore channel pattern;

s34, etching: after the treatment of step S33, the substrate is placed in an etching machine, and C is introduced₂F₆Performing dry etching on the silicon dioxide oxide film and the silicon substrate by ionization as working gas to form a pore channel with a set depth;

s35, removing the photoresist: after the treatment of step S34, the excess photoresist is removed by acetone and isopropanol in sequence, and then the substrate is cleaned by deionized water and dried.

Technical Field

The invention belongs to information security and semiconductor devices, relates to a structural design which can be integrated with a core chip or a micro-electromechanical device (MEMS) and has a self-destruction function and a preparation method thereof, and particularly relates to a secondary excitation self-destruction chip based on an array type pore channel and a preparation method thereof.

Background

With the rapid development of modern information technology, various semiconductor devices based on semiconductor materials such as silicon, gallium nitride and the like are widely applied in links of information acquisition, analysis, storage, transmission and the like in the military and civil fields, and some information terminal devices inevitably store a large amount of core data. If the information terminal equipment is lost, stolen and the like, important information stored in the storage chip can be stolen and divulged, so that a self-destruction function needs to be added to the important chips such as the storage chip and the like during product planning and design to ensure that the core chip can be destroyed in an emergency to protect the information from being leaked. In addition, the precise MEMS device embodies the delicate design concept of the designer, and also needs to integrate a corresponding self-destruction structure to prevent the MEMS device from being broken and copied.

At present, a chip self-destruction design mostly adopts a strong pulse current impact method, and a chip circuit is broken down by using instantly conducted strong pulse current so as to lose the function of the chip circuit, but the chip is not completely destroyed because only a small area is broken down, the whole structure is still maintained, and the stored information still has the possibility of partial recovery. The chip can be completely destroyed only by adopting a physical or chemical method to completely destroy the physical structure or the functional layer of the chip, and the information can not be recovered. The 200480013540.8 patent discloses a device structure for etching a storage medium with a reactant chemical, but the structure is complicated in design and has poor safety and reliability.

In conclusion, the development of the self-destruction chip which has high safety and reliability and can completely self-destroy the chip with important information to ensure the information safety has important significance for the information safety guarantee of the chip in the field.

Disclosure of Invention

The invention aims to solve the problems and provides a secondary excitation self-destruction chip based on array type pore channels and a preparation method thereof.

In order to achieve the purpose, the invention provides a two-stage excitation self-destruction chip based on array type pore channels, which comprises a substrate layer and a self-destruction structure;

the substrate layer is a target chip;

the self-destruction structure is arranged on the back of the target chip and comprises a heating circuit, a plurality of pore channels and an energetic material layer, the pore channels are arranged in a to-be-destroyed area on the target chip in an array mode, the energetic material layer covers a heating area of the heating circuit and at least part of the pore channel array area, and the heating circuit is connected in series in a circuit loop formed by an external control unit and a power supply unit.

The array pore channel-based secondary excitation self-destruction chip comprises a silicon substrate and a target circuit arranged on the silicon substrate. The target circuit herein is designed to implement a certain function, such as storage, logical operation, logical control, and the like. The target circuit is not modified in the invention, and any chip which is related to the field and carries the target circuit with any function can be used as the target chip of the invention. Similarly, the target chip may be prepared in a conventional manner without any particular limitation.

The external control unit comprises a photosensitive switch or/and a force-sensitive switch, and two ends of the photosensitive switch or/and the force-sensitive switch are respectively connected to the heating circuit and the power supply unit. When the external control unit simultaneously comprises the photosensitive switch and the force sensitive switch, the photosensitive switch and the force sensitive switch are connected in parallel and then connected into the heating circuit, and are connected with the power supply unit. The photosensitive switch and the force sensitive switch are used as preset trigger conditions, when the packaging tube shell of the chip is subjected to unauthorized opening, the force sensitive switch can sense the change of fastening force when the packaging body is opened to conduct the heating circuit, and meanwhile, as a parallel trigger mechanism, the photosensitive switch can sense the brightness change inside the packaging body to conduct the heating circuit on the back of the core chip. After the heating circuit is loaded with current, a hot area is formed locally and an explosion reaction is triggered, and a huge impact force is formed in the sealed packaging shell instantly, so that the target chip is destroyed quickly and accurately, and the core information is prevented from being stolen. It should be noted that the preset trigger condition may be only a light-sensitive switch or a force-sensitive switch, and the trigger condition is not limited to the light-sensitive switch and the force-sensitive switch. Moreover, the preset trigger condition can adopt other conventional settings in the field, for example, a corresponding self-destruction program and a circuit are arranged in the chip, so that the chip automatically conducts the heating circuit after receiving the command; or triggering a self-destruction program of the chip by using laser, and the like. The invention adopts a two-stage parallel trigger mechanism consisting of a photosensitive switch and a force sensitive switch, and is simple and easy to implement.

According to the array-type pore channel-based secondary excitation self-destruction chip, the heating circuit is mainly used for heating the energetic material layer, and on the basis that the energetic material layer can be heated to be exploded by the energetic material, a person skilled in the art can correspondingly design the heating circuit according to actual conditions. According to the invention, the heating circuit comprises an electrode pad, two metal wires and a heating wire, the electrode pad comprises an anode pad and a cathode pad, the anode pad and the cathode pad are respectively connected with one metal wire, the end parts of the two ends of the heating wire are respectively connected with the two metal wires, the anode pad and the cathode pad are respectively connected with an external control unit and a power supply unit, and the heating wire is a heating area of the heating circuit.

According to the array type pore channel-based secondary excitation self-destruction chip, the heating wire is mainly used for providing excitation energy for the energetic material, the specific size of the heating wire is designed on the basis of providing corresponding excitation energy, and the parameters of the conventional heating wire in the field can be referred. The width of the heating wire is preferably 2-50 microns, the length of the wire is 500-50000 microns (bending setting), the aspect ratio is 200-5000, and the thickness of the wire is 200-1000 nanometers, further preferably the width is 2-10 microns, the aspect ratio is 500-1000, and the thickness of the wire is 200-1000 nanometers.

The heating circuit can be made of conventional materials such as aluminum, copper and the like, and can also be made of alloy materials with high melting point, such as NiCr alloy or W alloy. The chip is typically a silicon substrate. In order to improve the bonding strength between the metal electrode such as aluminum, copper and the like and the silicon substrate and form good interface bonding force, an annealing process is usually performed, which also causes the electrical properties of the electrode to be reduced due to the interdiffusion between the metal electrode and Si. In order to prevent the interdiffusion phenomenon, a barrier layer is preferably arranged between the silicon substrate and the heating circuit (metal electrode), the barrier layer is a silicon nitride or silicon dioxide film, and the interdiffusion between the silicon substrate and the metal electrode is prevented, so that the heating chip can bear higher heating temperature, and the temperature and the reliability of a hot zone of the heating circuit are improved.

The secondary excitation self-destruction chip based on the array pore channels, the deep holes and other three-dimensional structures are designed to reduce the strength of a matrix, so that the damage of the target chip in a smashing manner is realized, and meanwhile, the introduction of the porous array structure can also reduce the dosage of a blasting agent and the area of the chip, realize the directional fixed-point damage and improve the damage effect. In order to ensure good self-destruction effect, the conventional method is to increase the filling amount of the energetic material, and the binding force is reduced and the energetic material is easy to fall off due to too high coating thickness, so that the chip area is inevitably increased by limiting the coating thickness. The invention adopts the porous silicon array structure design, the energetic material is filled into the pore canal to have better self-destruction effect, and in addition, the bonding force between the energetic material coating and the chip is better because the energetic material is filled into the pore canal. The shape of the energetic material layer is not particularly limited and may take the form of, but not limited to, circles, squares, or other irregular shapes. The energetic material layer may cover a portion of the cell array region or the entire cell array region. Preferably, the pore spacing of the pore canal array is 20-200 microns; the pore diameter width of the pore channel is 10-100 microns, and the depth of the pore channel is 20-200 microns. The shape of the pore passage is not particularly limited, and it may take the form of, but not limited to, a circle, a rectangle, or a regular polygon.

According to the array type pore channel based secondary excitation self-destruction chip, the energy-containing material layer covers the pore channel array and the heating area of the heating circuit, and when the energy-containing material layer is heated, severe explosion reaction occurs on the energy-containing material, so that strong impact is instantaneously generated on a target chip in a closed packaging shell, and the target chip is thoroughly destroyed in a penetrating or crushing manner. I.e. the energetic material mainly functions as chemical blasting, and the energetic material which is conventional in the field can be adopted. In the invention, the energetic material is preferably lead stevensite.

The secondary excitation self-destruction chip based on the array type pore channel is based on the design idea of physical destruction, the secondary excitation structure design of weak current excitation-chemical explosion is adopted, when the preset trigger condition is met, the self-destruction program of the chip is activated, the excitation circuit is conducted to release heat, the energetic material pre-embedded in the pore channel at the back of the target chip is heated to generate violent explosion reaction, and strong impact is generated on the target chip in the closed packaging shell instantly, so that the target chip is thoroughly destroyed in a penetrating or crushing mode. The penetrating or crushing physical damage has non-restorability and the damage effect is more complete. The self-destruction structure on the self-destruction chip is mainly used in the field of information security, and particularly can perform unrecoverable and thorough physical destruction on semiconductor-based devices such as a core memory chip and a key MEMS device.

The invention also provides a preparation method of the array-type pore channel-based secondary excitation self-destruction chip, which mainly comprises the following steps:

s1, preparing an insulating layer on the back of the substrate, and depositing a metal conducting layer on the surface of the insulating layer;

s2, etching the metal conductive layer into a heating circuit by adopting a photoetching process;

s3, etching a pore array on the substrate by adopting a photoetching process according to the region to be damaged, wherein the pore array covers the region to be damaged of the target chip;

s4, coating an energetic material layer on the back of the target chip by adopting a coating process, wherein the energetic material layer covers a heating area of the heating circuit and at least part of the pore array area;

s5, the heating circuit may be connected to an external control unit and a power supply unit.

In the preparation method of the array-type pore channel-based secondary excitation self-destruction chip, in the step S1, the insulating layer and the metal conductive layer are prepared by adopting conventional preparation methods and parameters in the field, and no special requirements are required. In the invention, the insulating layer is preferably prepared on the substrate by a thermal oxidation or chemical vapor deposition process, and the metal conducting layer is deposited on the surface of the insulating layer by a magnetron sputtering or evaporation process. In general, the base material of the substrate can adopt a silicon single crystal substrate which is conventional in the field, the insulating layer is a silicon dioxide or silicon nitride insulating layer, the thickness is 10-200nm, and a thermal oxidation process is further optimized to prepare a silicon dioxide oxide film; the metal conducting layer is preferably an aluminum conducting layer and a copper conducting layer, and the thickness is 200-1000 nm. Further, the processes such as the photolithography process, the plasma dry etching process and the like involved in the steps can all adopt conventional parameters in the field, and are not particularly limited.

In the present invention, the step S1 specifically includes the following steps:

s11, cleaning preparation: cleaning and drying a substrate containing a silicon substrate for later use;

s12, preparing an oxide film: after the treatment of step S11, the substrate is placed in a thermal oxidation furnace, the cavity of the oxidation furnace is sealed and vacuumized to be lower than 10 DEG^-1Pa, introducing oxygen, heating the heating furnace body to 1050-1150 ℃ at the temperature rising rate of 15-25 ℃/min, preserving the heat for 10-20 minutes, cooling to below 400 ℃ at the temperature falling rate of 15-25 ℃/min, and naturally cooling to roomForming a silicon dioxide oxide film;

s13, coating: after the treatment of the step S12, the substrate is placed on a sample table of a film coating machine and is vacuumized to 10 DEG^-3Pa below, at 15-25cm³Argon is filled to 0.2-0.8Pa at the flow rate of/min, sputtering coating is carried out on the metal target material to form a metal film, the coating time is 5-20min, and then the metal film is naturally cooled to the room temperature.

In the step S11, the substrate may be cleaned and dried by conventional methods in the art, preferably by ultrasonic cleaning with acetone, ethanol, and deionized water for 10-20 minutes, taking out, and then dehydrating and baking at 350 ℃ in nitrogen atmosphere. The metal target is aluminum or copper.

In the present invention, the step S2 specifically includes the following steps:

s21, gluing, spinning and soft drying: placing the coated substrate on a glue spreader, dripping glue, then performing glue throwing, heating to 100-120 ℃ in vacuum, and performing soft drying treatment for 30-60 seconds;

s22, exposure and postbaking: after the processing of the step S21, placing the substrate on a sample platform of an exposure machine, copying a heating circuit diagram on the photoresist, and then placing the substrate in an environment with the temperature of 110-;

s23, developing and hard baking: after the processing of the step S22, spraying the developing solution on the surface of the substrate for developing, then placing the substrate in an environment with the temperature of 110-130 ℃ for heat preservation for 1-3min for hard baking treatment, and exposing the heating circuit pattern;

s24, etching: after the treatment of the step S23, putting the substrate in an etching machine, introducing chlorine gas as working gas for ionization to carry out dry etching on the metal film, and removing the exposed redundant metal film;

s25, removing the photoresist: after the treatment of step S24, the excess photoresist is removed by acetone and isopropanol in sequence, and then the substrate is cleaned and dried by deionized water.

In the step S2, in step S21, the substrate can be rotated at a low speed during the dispensing process, and then accelerated to 2800 and 3200rpm for spin coating after the dispensing process. After the photoresist is removed in step S25, the quality of the heating circuit can be checked by a microscope to ensure that the heating area is not broken.

The step S3 specifically includes the following steps:

s31, gluing, spinning and soft drying: after the treatment of the step S25, placing the substrate on a glue spreader, dripping glue, then performing glue throwing, heating to the temperature of 100-;

s32, exposure and postbaking: after the treatment of the step S31, the substrate is placed on a sample platform of an exposure machine, the pore pattern is copied on the photoresist, and then the substrate is placed in an environment with the temperature of 110-;

s33, developing and hard baking: after the treatment of the step S32, spraying the developing solution on the surface of the substrate for development, and then placing the substrate in an environment with the temperature of 110-130 ℃ for heat preservation for 1-3min for hard baking treatment to expose the pore channel pattern;

s34, etching: after the treatment of step S33, the substrate is placed in an etching machine, and C is introduced₂F₆Performing dry etching on the silicon dioxide oxide film and the silicon substrate by ionization as working gas to form a pore channel with a set depth;

s35, removing the photoresist: after the treatment of step S34, the excess photoresist is removed by acetone and isopropanol in sequence, and then the substrate is cleaned and dried by deionized water.

In the step S3, in step S31, the substrate can be rotated at a low speed during the dispensing process, and then accelerated to 2800 and 3200rpm for spin coating after the dispensing process. And step S35, after the photoresist is removed, using a microscope to check the etching quality of the pore channel, and ensuring that the pore channel reaches the corresponding design size and the coverage area.

In the preparation method of the array-type pore channel-based secondary excitation self-destruction chip, the coating process involved in step S4 may be, but is not limited to, a screen printing or a dispensing process. After the energetic material is coated, the coating can be dried at the low temperature of 30-50 ℃.

In the above method for preparing the array-type pore channel-based secondary excitation self-destruction chip, when the external control unit is formed by the photosensitive switch or/and the force-sensitive switch and used as a preset trigger condition, in step S5, the photosensitive switch or/and the force-sensitive switch is connected between the power supply unit and the heating circuit, and then the chip is packaged. When the external control unit simultaneously comprises the photosensitive switch and the force sensitive switch, the photosensitive switch and the force sensitive switch need to be connected in parallel first and then connected between the power supply unit and the heating circuit.

It should be noted that the innovation point and the protection point of the secondary excitation self-destruction chip based on the array type pore channel and the preparation method thereof provided by the invention lie in the self-destruction structure and the preparation method of the self-destruction structure, and the preparation of the target chip only needs to be prepared by adopting a conventional preparation method, and the circuit structure of the target chip is not limited at all, such as an MEMS structure and the like. The self-destruction structure provided by the invention can be prepared firstly, and then the preparation of the target chip is carried out. Or the circuit structure of the target chip can be prepared firstly and then the self-destruction structure can be prepared. In the present invention, it is preferable that the target chip circuit structure is prepared after the self-destruction structure is prepared.

Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects:

(1) the array type pore channel-based secondary excitation self-destruction chip provided by the invention adopts a secondary excitation structure design of weak current excitation-chemical explosion, when a preset trigger condition is met, a self-destruction program of the chip is activated, an excitation circuit is conducted to release heat, an energetic material embedded in a pore channel at the back of a target chip is heated to generate a violent explosion reaction, and a strong impact is instantaneously generated on the target chip in a closed packaging shell, so that the target chip is completely destroyed in a penetrating or crushing way, the penetrating or crushing physical damage has irrecoverability, the damage effect is more thorough, and the information safety of the target chip is ensured.

(2) According to the array-type pore channel-based secondary excitation self-destruction chip, the pore channel, the deep hole and other three-dimensional structures are designed on the semiconductor substrate to reduce the strength of the substrate, and meanwhile, the dosage of the blasting agent and the area of the chip can be reduced, so that directional fixed-point damage is realized, and the effect of crushing the target chip is achieved under the working condition of low power consumption.

(3) The array-type-pore-channel-based secondary excitation self-destruction chip provided by the invention adopts a triggering mechanism consisting of the photosensitive switch and the force sensitive switch, can realize quick self-destruction of the core chip during unauthorized dissection, and can effectively ensure the safety of important sensitive information and key chip technology.

(4) The array-type pore passage-based secondary excitation self-destruction chip provided by the invention has the advantages that the self-destruction structure is manufactured on the substrate through photoetching and film coating methods, and the photosensitive switch and the force sensitive switch are integrated with the target chip, so that the single-tube shell integration of the whole self-destruction chip is realized, the processing change of the original chip is small, and the controllability is high.

(5) The array-type-pore-channel-based secondary excitation self-destruction chip and the preparation method thereof have the advantages of high secrecy, miniaturization, low power consumption, high controllability and the like, are safe and reliable, have high technical maturity, are small in processing change of the original chip, are wide in application range, are mature in preparation process, are easy to operate, are easy to industrialize, and are worthy of popularization.

Drawings

FIG. 1 is a schematic view of a self-destruction structure in example 1;

FIG. 2 is a schematic structural diagram of a self-destruct chip (photosensitive switch and force-sensitive switch are not shown) in example 1;

fig. 3 is a schematic view of a self-destruct chip package structure in embodiment 1;

FIG. 4 is a diagram illustrating the self-destruction effect of the self-destruction chip provided in embodiment 1; wherein, (a) is a packaged picture before self-destruction, and (b) is a chip damaged picture after self-destruction.

Description of reference numerals: 1. an electrode pad; 2. a metal wire; 3. heating wires; 4. a duct; 5. a target chip; 6. a layer of energetic material; 7. a light sensitive switch; 8. a force sensitive switch; 9. a power source.

Detailed Description

So that the technical solutions of the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings, it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, belong to the present invention.

Example 1

In this embodiment, the two-stage self-destruction chip based on the array-type pore channels is shown in fig. 1-3. The array-type pore channel-based secondary excitation self-destruction chip comprises a substrate layer and a self-destruction structure.

The base layer is the target chip 5.

The self-destruction structure is arranged on the back of the target chip 5 and comprises a heating circuit, a plurality of pore channels 4, an energetic material layer 6, a photosensitive switch 7, a force-sensitive switch 8 and a power supply 9. The pore channels 4 are arranged in an array in a to-be-damaged area on the target chip 5, and the energetic material layer 6 covers a heating area of the heating circuit and a part of the pore channel array area.

The heating circuit comprises an electrode pad 1, two metal wires 2 and a heating wire 3, wherein the electrode pad 1 comprises an anode pad and a cathode pad, the anode pad and the cathode pad are respectively connected with one metal wire 2, the end parts of the two ends of the heating wire 3 are respectively connected with the two metal wires 2, the anode pad and the cathode pad are respectively connected with an external control unit and a power supply unit (namely a power supply), and the heating wire 3 is a heating area of the heating circuit. The heating wire 3 has a width of 4 μm, a length of 2000 μm, an aspect ratio of 500 and a thickness of 500 nm.

The hole pitch of the pore canal array is 50 μm; the cross-section of the cell channels 4 is 10 x 10 μm square and the depth of the cell channels 4 is 50 μm. The overall size of the array is 5 x 5 mm.

The energetic material layer 6 is a Stefin lead acid coating; the cross section of the round bar is circular with the diameter of 4 mm, and the thickness of the round bar is 0.3 mm.

The external control unit comprises a light sensitive switch 7 and a force sensitive switch 8. The photosensitive switch 7 and the force sensitive switch 8 are connected in parallel, the anode of the power supply 9 is connected to the anode bonding pad through a gold thread after being connected with the photosensitive switch 7 and the force sensitive switch 8 in parallel, and the cathode of the power supply is connected with the cathode bonding pad through the gold thread.

Example 2

In the following, the preparation method of the array-type pore channel-based secondary excitation self-destruction chip provided in example 1 is described, in this embodiment, the base material of the substrate is a silicon single crystal substrate, and the specific steps are as follows:

s1, providing a silicon single crystal substrate, preparing an insulating layer on the back of the silicon single crystal substrate, and depositing a metal conducting layer on the surface of the insulating layer:

s11, cleaning preparation: cleaning a silicon single crystal substrate, respectively ultrasonically cleaning the silicon single crystal substrate for 10min by using acetone, ethanol and deionized water in sequence, taking out the silicon single crystal substrate, dehydrating and baking the silicon single crystal substrate at 300 ℃ in a nitrogen atmosphere for drying for later use;

s12, preparing an oxide film: after the processing of step S11, vertically placing the silicon single crystal substrate on a sample holder, pushing into a thermal oxidation furnace, sealing the cavity of the oxidation furnace and vacuumizing to less than 10%^-1Pa, introducing oxygen, heating the heating furnace body to 1100 ℃ according to the heating rate of 15 ℃/min, preserving the heat for 10min, cooling to 400 ℃ according to the cooling rate of 15 ℃/min, and naturally cooling to room temperature;

s13, coating: after the treatment of step S12, the silicon single crystal substrate is placed on a sample platform of a film plating machine and is vacuumized to 10 degrees^{- 3}Pa below, at 20cm³Argon is filled to 0.5Pa at the flow rate of/min, a direct current sputtering power supply is started to sputter and coat the aluminum target to form an aluminum film, the coating time is 10min, and then the aluminum film is naturally cooled to the room temperature.

S2, etching the metal conductive layer into a heating circuit by adopting a photoetching process:

s21, gluing, spinning and soft drying: after the treatment of the step S13, placing the coated silicon single crystal substrate on a glue spreader, rotating at a low speed and dripping glue, rotating at an accelerated speed to 3000rpm for glue throwing, then heating to 110 ℃ in vacuum, and preserving heat for 45S for soft drying;

s22, exposure and postbaking: after the processing of the step S21, the silicon single crystal substrate is placed on a sample platform of an exposure machine, pre-alignment is carried out through laser positioning, a preset exposure program is started to copy a heating circuit pattern on a photoetching plate on photoresist, and then the silicon single crystal substrate is placed in an environment with the temperature of 120 ℃ for heat preservation for 1min to carry out post-baking processing;

s23, developing and hard baking: after the processing of the step S22, spraying a developing solution on the surface of the silicon single crystal substrate rotating at a low speed of 300rmp through a multi-nozzle for development, then placing the silicon single crystal substrate in an environment of 120 ℃ for heat preservation for 1.5min for hard baking treatment, and exposing the heating circuit pattern;

s24, etching: after the treatment of the step S23, the silicon single crystal substrate is placed in an etching machine, and the introduced chlorine is ionized to carry out dry etching on the aluminum film to remove the exposed redundant metallic aluminum;

s25, removing the photoresist: after the treatment of the step S24, removing the redundant photoresist by using acetone and isopropanol in sequence, and then cleaning and drying the silicon single crystal substrate by using deionized water;

s26, checking: after the processing of step S25, the quality of the heating circuit is checked with a microscope to ensure that the heating area is not broken.

S3, etching a pore array window in a blank area beside the heating circuit by adopting a photoetching process according to the target chip quasi-damage area, wherein the pore array window covers the target chip quasi-damage area, and etching the pore array window into a pore array by adopting a plasma dry etching process;

s31, gluing, spinning and soft drying: after the treatment of the step S26, placing the silicon single crystal substrate on a glue spreader, rotating at a low speed and dripping glue, rotating at an accelerated speed to 3000rpm for glue throwing, then heating to 110 ℃ in vacuum, and preserving heat for 45S for soft drying;

s32, exposure and postbaking: after the processing of the step S31, placing the silicon single crystal substrate on a sample platform of an exposure machine, pre-aligning through laser positioning, starting a preset exposure program to copy the pore channel patterns on the photoetching plate on the photoresist, then placing the photoresist in an environment of 120 ℃ for heat preservation for 1min for post-baking treatment, wherein the pore channel patterns are square pore channel arrays of 10 multiplied by 10 microns, the pore space is 50 microns, and the arrays form a window of 5 multiplied by 5 mm;

s33, developing and hard baking: after the treatment of the step S32, spraying a developing solution on the surface of the silicon single crystal substrate rotating at a low speed of 300rmp through a multi-nozzle for development, and then placing the silicon single crystal substrate in an environment at 120 ℃ for heat preservation for 1.5min for hard baking treatment to expose the pore channel pattern;

s34, etching: after the treatment of step S33, the sample is placed in an ion etcher, and C is introduced₂F₆The working gas is ionized to carry out dry etching on the silicon dioxide protective layer and the silicon substrate to form a deep layerPore channels with the size of 50 mu m;

s35, removing the photoresist: after the treatment of the step S34, removing the redundant photoresist by using acetone and isopropanol in sequence, and then cleaning and drying the silicon single crystal substrate by using deionized water;

s36, checking: after the processing of the step S35, checking the etching quality of the pore canal by using a microscope to ensure that the pore canal meets the preset design;

s4, coating the back of the silicon single crystal substrate by adopting a drop coating process to form an energetic material layer with the diameter of 4 mm and the thickness of 0.3mm, wherein the energetic material layer covers a heating area of a heating circuit and a part of pore array area;

and S5, connecting the photosensitive switch and the force sensitive switch in parallel, connecting one end of the photosensitive switch and the force sensitive switch to an anode pad of the heating circuit through a gold wire, connecting the other end of the photosensitive switch and the force sensitive switch to an anode of the power supply through the gold wire, connecting a cathode of the power supply to a cathode pad through the gold wire, and then packaging.

This embodiment mainly uses a silicon single crystal substrate as an example to explain the method for preparing the self-destruction structure provided by the present invention in detail. When it is necessary to prepare the circuit structure of the target chip, the step S36 is followed, taking the MEMS structure of the target chip as an example: the MEMS structure of the target chip is prepared on the other side (namely the front side) of the silicon single crystal substrate by a conventional means, the silicon single crystal substrate is cut into single chips by adopting a laser scribing process, and then gold wires led out from a positive electrode bonding pad and a negative electrode bonding pad are taken as related pins of a circuit positive electrode and a circuit negative electrode of the target chip.

The self-destruction principle and process of the array-type pore channel-based secondary excitation self-destruction chip provided by the embodiment are described as follows: when the packaging tube shell of the chip is subjected to unauthorized opening, the force sensitive switch can sense the change of fastening force when the packaging body is opened to conduct the heating circuit, and meanwhile, as a parallel trigger mechanism, the light sensitive switch can sense the brightness change in the packaging body to conduct the heating circuit on the back of the target chip. After the heating circuit on the back of the target chip is loaded with current, a hot area is formed locally and an energetic material is excited to cause an explosion reaction, huge impact force is formed in a closed packaging shell instantly, and irreparable comminuted self-destruction damage is realized on the core electronic chip, so that the target chip is destroyed quickly and accurately, and core information is prevented from being stolen.

The self-destruction chip provided in example 1 was subjected to a self-destruction experiment, and the silicon single crystal substrate having the self-destruction structure prepared thereon was connected to an existing printed circuit board and sealed and fixed by a steel sheet and a sealing ring to simulate the state in which the chip was sealed. The pressure switch and the photosensitive switch are switched on, and the results before and after the experiment are shown in FIG. 4. As can be seen, after the current is applied, the chip is blown away and a crushing damage effect is formed.

In summary, the self-destruction structure provided by the invention is a structure which can be integrated with a core chip or a Micro Electro Mechanical System (MEMS) and has a self-destruction function, and is based on a design idea of physical destruction, a secondary excitation structure design of weak current excitation-chemical explosion is adopted, and by integrating a trigger device and an explosion material at a chip level, when a preset trigger condition is met, a self-destruction program of the chip is activated, a heating circuit is conducted to release heat, an energetic material is excited to cause an explosion reaction, and irreparable self-destruction damage is realized on a target chip. The technology has the characteristics of high secrecy, miniaturization, low power consumption, high controllability and the like, can realize the quick self-destruction of the core chip during unauthorized dissection, and can effectively ensure the safety of important sensitive information and key chip technology. The explosion type self-destruction technology based on the energetic material has the advantages of safety, reliability, high technical maturity, small modification on the original chip processing and wide application range, and is a self-destruction mode with high technical feasibility at present.

It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.